The main purpose for large page usage is to improve system performance for high performance computing (HPC) applications or any memory-access-intensive application that uses large amounts of virtual memory. The improvement in system performance stems from the reduction of translation lookaside buffer (TLB) misses due to the ability of the TLB to map to a larger virtual memory range.
Large pages also improve memory prefetching by eliminating the need to restart prefetch operations on 4 KB boundaries. AIX® supports large page usage by both 32-bit and 64-bit applications.
The POWER4 large page architecture requires all the virtual pages in a 256 MB segment to be the same size. AIX supports this architecture by using a mixed mode process model such that some segments in a process are backed with 4 KB pages, while other segments are backed with 16 MB pages. Applications can request that their heap segments or memory segments be backed with large pages. For detailed information, refer to Application configuration for large pages.
AIX maintains separate 4 KB and 16 MB physical memory pools. You can specify the amount of physical memory in the 16 MB memory pool using the vmo command. The large page pool is dynamic, so the amount of physical memory that you specify takes effect immediately and does not require a system reboot. The remaining physical memory backs the 4 KB virtual pages.
# chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE <user id>