Extended mnemonics for branch prediction
The assembler source program can have information on branch conditional instruction by adding a branch prediction suffix to the mnemonic of the instruction.
If the likely outcome (branch or fall through) of a given Branch Conditional instruction is known, the programmer can include this information in the assembler source program by adding a branch prediction suffix to the mnemonic of the instruction. The assembler uses the branch prediction information to determine the value of a bit in the machine instruction. Using a branch prediction suffix may improve the average performance of a Branch Conditional instruction.
The following suffixes can be added to any Branch Conditional mnemonic, either basic or extended:
| Item | Description |
|---|---|
| + | Predict branch to be taken |
| - | Predict branch not to be taken (fall through) |
The branch prediction suffix should be placed immediately after the rest of the mnemonic (with no separator character). A separator character (space or tab) should be used between the branch prediction suffix and the operands.
If no branch prediction suffix is included in the mnemonic, the assembler uses the following default assumptions in constructing the machine instruction:
- For relative or absolute branches ( bc[l][a]) with negative displacement fields, the branch is predicted to be taken.
- For relative or absolute branches ( bc[l][a]) with nonnegative displacement fields, the branch is predicted not to be taken (fall through predicted).
- For branches to an address in the LR or CTR (bclr[l]) or (bcctr[l]), the branch is predicted not to be taken (fall through predicted).
The portion of the machine instruction which is controlled by the branch prediction suffix is the y bit of the BO field. The y bit is set as follows:
- Specifying no branch prediction suffix, or using the suffix which is the same as the default assumption causes the y bit to be set to 0.
- Specifying a branch prediction suffix which is the opposite of the default assumption causes the y bit to be set to 1.
The following examples illustrate use of branch prediction suffixes:
- Branch if CR0 reflects condition less than. Executing the instruction
will usually result in branching.
blt+ target - Branch if CR0 reflects condition less than. Target address is
in the Link Register. Executing the instruction will usually result
in falling through to the next instruction.
bltlr-
The following is a list of the Branch Prediction instructions that are supported by the AIX® assembler:
bc+ bc- bca+ bca-
bcctr+ bcctr- bcctrl+ bcctrl-
bcl+ bcl- bcla+ bcla-
bclr+ bclr- bclrl+ bclrl-
bdneq+ bdneq- bdnge+ bdnge-
bdngt+ bdngt- bdnle+ bdnle-
bdnlt+ bdnlt- bdnne+ bdnne-
bdnns+ bdnns- bdnso+ bdnso-
bdnz+ bdnz- bdnza+ bdnza-
bdnzf+ bdnzf- bdnzfa+ bdnzfa-
bdnzfl+ bdnzfl- bdnzfla+ bdnzfla-
bdnzflr+ bdnzflr- bdnzflrl+ bdnzflrl-
bdnzl+ bdnzl- bdnzla+ bdnzla-
bdnzlr+ bdnzlr- bdnzlrl+ bdnzlrl-
bdnzt+ bdnzt- bdnzta+ bdnzta-
bdnztl+ bdnztl- bdnztla+ bdnztla-
bdnztlr+ bdnztlr- bdnztlrl+ bdnztlrl-
bdz+ bdz- bdza+ bdza-
bdzeq+ bdzeq- bdzf+ bdzf-
bdzfa+ bdzfa- bdzfl+ bdzfl-
bdzfla+ bdzfla- bdzflr+ bdzflr-
bdzflrl+ bdzflrl- bdzge+ bdzge-
bdzgt+ bdzgt- bdzl+ bdzl-
bdzla+ bdzla- bdzle+ bdzle-
bdzlr+ bdzlr- bdzlrl+ bdzlrl-
bdzlt+ bdzlt- bdzne+ bdzne-
bdzns+ bdzns- bdzso+ bdzso-
bdzt+ bdzt- bdzta+ bdzta-
bdztl+ bdztl- bdztla+ bdztla-
bdztlr+ bdztlr- bdztlrl+ bdztlrl-
beq+ beq- beqa+ beqa-
beqctr+ beqctr- beqctrl+ beqctrl-
beql+ beql- beqla+ beqla-
beqlr+ beqlr- beqlrl+ beqlrl-
bf+ bf- bfa+ bfa-
bfctr+ bfctr- bfctrl+ bfctrl-
bfl+ bfl- bfla+ bfla-
bflr+ bflr- bflrl+ bflrl-
bge+ bge- bgea+ bgea-
bgectr+ bgectr- bgectrl+ bgectrl-
bgel+ bgel- bgela+ bgela-
bgelr+ bgelr- bgelrl+ bgelrl-
bgt+ bgt- bgta+ bgta-
bgtctr+ bgtctr- bgtctrl+ bgtctrl-
bgtl+ bgtl- bgtla+ bgtla-
bgtlr+ bgtlr- bgtlrl+ bgtlrl-
ble+ ble- blea+ blea-
blectr+ blectr- blectrl+ blectrl-
blel+ blel- blela+ blela-
blelr+ blelr- blelrl+ blelrl-
blt+ blt- blta+ blta-
bltctr+ bltctr- bltctrl+ bltctrl-
bltl+ bltl- bltla+ bltla-
bltlr+ bltlr- bltlrl+ bltlrl-
bne+ bne- bnea+ bnea-
bnectr+ bnectr- bnectrl+ bnectrl-
bnel+ bnel- bnela+ bnela-
bnelr+ bnelr- bnelrl+ bnelrl-
bng+ bng- bnga+ bnga-
bngctr+ bngctr- bngctrl+ bngctrl-
bngl+ bngl- bngla+ bngla-
bnglr+ bnglr- bnglrl+ bnglrl-
bnl+ bnl- bnla+ bnla-
bnlctr+ bnlctr- bnlctrl+ bnlctrl-
bnll+ bnll- bnlla+ bnlla-
bnllr+ bnllr- bnllrl+ bnllrl-
bns+ bns- bnsa+ bnsa-
bnsctr+ bnsctr- bnsctrl+ bnsctrl-
bnsl+ bnsl- bnsla+ bnsla-
bnslr+ bnslr- bnslrl+ bnslrl-
bnu+ bnu- bnua+ bnua-
bnuctr+ bnuctr- bnuctrl+ bnuctrl-
bnul+ bnul- bnula+ bnula-
bnulr+ bnulr- bnulrl+ bnulrl-
bnz+ bnz- bnza+ bnza-
bnzctr+ bnzctr- bnzctrl+ bnzctrl-
bnzl+ bnzl- bnzla+ bnzla-
bnzlr+ bnzlr- bnzlrl+ bnzlrl-
bso+ bso- bsoa+ bsoa-
bsoctr+ bsoctr- bsoctrl+ bsoctrl-
bsol+ bsol- bsola+ bsola-
bsolr+ bsolr- bsolrl+ bsolrl-
bt+ bt- bta+ bta-
btctr+ btctr- btctrl+ btctrl-
btl+ btl- btla+ btla-
btlr+ btlr- btlrl+ btlrl-
bun+ bun- buna+ buna-
bunctr+ bunctr- bunctrl+ bunctrl-
bunl+ bunl- bunla+ bunla-
bunlr+ bunlr- bunlrl+ bunlrl-
bz+ bz- bza+ bza-
bzctr+ bzctr- bzctrl+ bzctrl-
bzl+ bzl- bzla+ bzla-
bzlr+ bzlr- bzlrl+ bzlrl-