clcs (Cache Line Compute Size) instruction
Purpose
Places a specified cache line size in a general-purpose register.
Note: The clcs instruction is supported only in the POWER® family architecture.
Syntax
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | RT |
| 11-15 | RA |
| 16-20 | /// |
| 21-30 | 531 |
| 31 | Rc |
Description
The clcs instruction places the cache line size specified by RA into the target general-purpose register (GPR) RT. The value of RA determines the cache line size returned in GPR RT.
| Item | Description |
|---|---|
| Value of RA | Cache Line Size Returned in RT |
| 00xxx | Undefined |
| 010xx | Undefined |
| 01100 | Instruction Cache Line Size |
| 01101 | Data Cache Line Size |
| 01110 | Minimum Cache Line Size |
| 01111 | Maximum Cache Line Size |
| 1xxxx | Undefined |
Note: The value in GPR RT must lie between 64 and 4096, inclusive, or results will be undefined.
The clcs instruction has only one syntax form and does not affect the Fixed-Point Exception Register. If the Record (Rc) bit is set to 1, the Condition Register Field 0 is undefined.
Parameters
| Item | Description |
|---|---|
| RT | Specifies target general-purpose register where result of operation is stored. |
| RA | Specifies cache line size requested. |
Examples
The following code loads the maximum cache line size into GPR 4:
# Assume that 0xf is the cache
line size requested
.
clcs 4,0xf
# GPR 4 now contains the maximum Cache Line size.