General terms used with PowerVP
The following terms are used within PowerVP™ and are described here as they should be interpreted when using PowerVP. They are arranged in a logical reading order.
- System
- A physical system is the entire Power® System, including all resources for CPU, memory, storage, and so on. This physical system can contain one or more partitions, or virtual systems. Some refer to the system as a frame or a CEC. When referring to PowerVP, do not interchange the terms system (physical) and partition (virtual system).
- Partition
- A logical partition (LPAR) is the division of a system's resources, such that it can run independently with its own operating system. A physical system can have one or more LPARs (virtual systems). These LPARs can be dedicated or shared (capped or uncapped). A hypervisor, like PowerVP, manages these partitions. Refer to the PowerVM® topics in IBM® Knowledge Center for descriptions of these related terms (virtual system, entitlement, hardware thread, VIOS, dedicated donate, processor folding, partition types, and so on).
- Hardware node
- Except for the smallest Power Systems™, there is a componentization of the physical system into books, drawers, or nodes. For example, Power 770/780 has up to four drawers, Power 795 has up to eight books.
- Socket
- A socket is a physical connection on a Power System that connects to one processor module. These modules can be either an SCM (single chip module) or a DCM (dual chip module).
- Processor Module
- A processor module is an orderable physical entity that connects to a socket. These processor modules can be in the format of an SCM or a DCM. With POWER7®, these modules contain processor cores, caches, and other components. For POWER7, a DCM implies two processor chips.
- Chip
- A processor chip is physical integrated circuit that contains processor cores, or caches, or both. POWER7 chips contain up to eight cores with on-chip L1, L2, and L3 caches. POWER8® chips contain up to 12 cores with on-chip L1, L2, L3, and L4 caches. This document does not describe all Power System configurations; but there are significant differences between POWER4/5/6/7/8 chips as well as model footprints within those architecture families.
- Core
- A processor core is a single physical processing unit. With POWER7, up to eight of these cores exist on a single chip and with POWER8, up to 12 of these cores exist on a single chip. Each POWER7 core can have up to four hardware threads that are dispatched to it simultaneously using SMT4. while each POWER8 core can have up to eight hardware threads dispatched to it simultaneously using SMT8. These hardware threads can be called logical cores. A system is sometimes referred to by its total number of physical cores, for example, a 64-core system. LPARs can have an entitlement in terms of a number of cores.
- CPU
- CPU is used to collectively refer to the CPU resources (core, socket, chip, system) for an entity (partition, system) when you are referring to its metrics like CPU utilization, CPU time, CPU cycles. The term CPU is not used explicitly as a specific resource name as it is often confusing. Some refer a CPU to a socket, some to a processor module, and some to a processor core.
- Utilization
- Utilization is a base performance term that is the percentage of time that a resource is busy. It is normally in the form a percentage, typically from 0% to 100%. Of course, some shared LPARs might have a utilization of greater than 100% if it consumes more CPU resources from the shared pool than its entitlement states.
- CPU utilization
- This term is much more complex than you might expect. It can refer simply to the percentage of time that the CPU resources are busy. However, with the advent of SMT levels (more than one hardware thread that is dispatched to a core), multi-core systems, and complex processor pipes, CPU utilization becomes more complicated. Each operating system might provide and interpret CPU utilization differently. AIX® and IBM i provide utilizations that consider SMT levels and hardware thread dispatch conditions. From this, CPU utilization is rendered where a linear relationship is expected between system throughput and CPU utilization. This metric comes with many assumptions (sufficient other resources for that workload to scale, only true for the actual workload that is used to tune the utilization while other workloads might scale differently, and so on). Linux operating systems currently provide CPU utilizations that are based more on occupancy (hardware thread that occupies a given core). The more that you understand about this topic, the more you realize that other metrics are also needed to best understand your system or application (such as scaling characteristics, instructions consumed, run cycles consumed, contention issues).
- Powerbus (W, X, Y, Z, A, B, C)
- Powerbus links are a set of links or buses within Power Systems. Within PowerVP on a POWER7, those links that are labeled W, X, Y, or Z are links within a hardware node; those links that are labeled A or B are links between hardware nodes. On a POWER8, those links that are labeled X0, X1, X2, and X3 are links within a hardware node; those links that are labeled A0, A1, or A2 are links between hardware nodes. These Powerbus links carry data between a given chip and other resources outside that chip (cache, memory, I/O). PowerVP portrays these links and their utilizations. Having a higher Powerbus utilization implies that there is a higher rate of data transfer.
- Memory Controller (MC)
- The memory controller is a set of links that connects the memory to the socket. The MC buses carry data between the memory controller and the processor. PowerVP monitors and displays these links and their utilizations. A higher MC bus utilization implies that there is a higher rate of data transfer.
- I/O (GX or PHB) bus
- The I/O bus is a set of links or buses within a Power System that connect the I/O subsystems to the chip. On a POWER7, they are labeled GX; and on a POWER8, they are labeled PHB. These links carry data for storage I/O and network I/O. PowerVP portrays these links, their utilizations, as well as their inbound/outbound data rate. Having a higher GX/PHB bus utilization implies that there is a higher rate of data transfer.
- Cycles per instruction (CPI)
- CPI is a standard measurement of application efficiency. It is the number of cycles consumed divided by the number of (machine) instructions completed. Normally, a lower CPI is better than a higher CPI. A CPI can be measured for a core, a processor module, a hardware node, or an LPAR with PowerVP. From an LPAR perspective, you can break down CPU utilization, into CPI components (for example, load/store unit, fixed point, global completion table).
- CPI stack analysis
- CPU utilization can be broken down into CPI components. Load/Store Unit (LSU CPI) reflects the cycles consumed for accessing data (L1, cache, L2 cache, L3 cache, memory). Fixed Point (FXU CPI) reflects cycles that are consumed on running fixed point. Global Completion Table (GCT CPI) reflects cycles that are consumed waiting on the global completion table for pipelining out-of-order instruction execution. PowerVP analysis typically focuses on LSU CPI.
- LSU CPI stack analysis
- Normally the largest component of CPU utilization is the LSU CPI for OLTP applications. In other words, accessing data consumes most of the CPU resources. A characterization of the time that it accesses data from L1 cache, L2 cache, L3 cache, and memory; this also notes whether the accesses are for cache/memory for a chip or for another chip on the same processor module or hardware node or distant hardware node. On a POWER8, a L4 cache is also used.
