SoC drawer, SoC design for hardware acceleration, Part 1

Building today's software to become tomorrow's hardware engine

From the developerWorks archives

Sam Siewert

Date archived: December 19, 2016 | First published: June 06, 2006

System-on-chip (SoC) designs offer the opportunity to migrate functionality initially implemented in software and firmware into hardware acceleration engines and state machines. Reconfigurable SoCs based on processors in FPGA fabric, such as the PowerPC® 405 in the Xilinx Virtex-4, provide a platform for rapid migration of functionality from PowerPC software and firmware to the FPGA logic. Configurable application-specific integrated circuit (ASIC) SoCs can be optimized similarly over product revisions as SoC ASIC roadmap configurations are defined. This article examines methods for software design, specification, and implementation that will simplify future efforts to offload software functionality to hardware. Basic video and image processing algorithms provide working example algorithms for this article and the next.

This content is no longer being updated or maintained. The full article is provided "as is" in a PDF file. Given the rapid evolution of technology, some steps and illustrations may have changed.

Zone=Multicore acceleration
ArticleTitle=SoC drawer: SoC design for hardware acceleration, Part 1