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7 replies Latest Post - ‏2014-09-05T17:10:21Z by AdhemervalZanella2
ThinkOpenly
ThinkOpenly
40 Posts
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Pinned topic Application use of Power8 on-chip accelerators

‏2014-08-29T23:13:31Z |

The IBM Redbook entitled "Performance Optimization and Tuning Techniques for IBM Processors, including IBM POWER8" mentions:

On-chip accelerators, including on-chip encryption, compression, and random number
generation accelerators

Are there application-level APIs for exploiting these functions?

Updated on 2014-08-29T23:13:44Z at 2014-08-29T23:13:44Z by ThinkOpenly
  • Bill_Buros
    Bill_Buros
    151 Posts
    ACCEPTED ANSWER

    Re: Application use of Power8 on-chip accelerators

    ‏2014-09-03T18:23:53Z  in response to ThinkOpenly

    A good question..    we'll poke around on that

    For readers - the Redbook referenced is easily found with search engines, but here's the direct link

    http://www.redbooks.ibm.com/abstracts/sg248171.html?Open

     

  • AdhemervalZanella2
    AdhemervalZanella2
    6 Posts
    ACCEPTED ANSWER

    Re: Application use of Power8 on-chip accelerators

    ‏2014-09-03T20:31:50Z  in response to ThinkOpenly

    Hi

    "On-chip accelerators, including on-chip encryption, compression, and random number"

    The ones provided by new ISA 2.07 hardware instructions, the more straightforward way to use them is through compiler builtints. Newer GCC version (4.8 and 4.9) have the new compiler directives [1] and you can use as __builtin_<instruction>.

    For more high level API, there is some attempts to add these instruction usage on OpenSSL [2], however latest version (1.0.0-i) still does not contain such changes. I don't know exactly the status of this patch submission. I know we have plans to submit same optimization to other projects (gnutls).

    IBM J9 already supports it and it is enable by default where applicable.

     

    Now, there is the POWER7+ offchips accelerators that are handled only through hypervisor calls. I know there is support for PowerVM already available, however I think support it is pending for PowerVM and PowerKVM. However, since they are only handled by kernel, its usage is limited (IPSEC, disk encription and zswap I think).

     

    They are the POWER7+ offchips accerators 

    [1] https://gcc.gnu.org/ml/gcc-patches/2013-05/msg01122.html

    [2] http://openssl.6102.n7.nabble.com/PATCH-0-4-Initial-POWER8-support-td47409.html