Topic
  • 2 replies
  • Latest Post - ‏2014-08-14T15:44:25Z by Bill_Buros
PowerLinuxFAQ
PowerLinuxFAQ
18 Posts

Pinned topic Taking advantage of POWER8 crypto co-processors

‏2014-08-14T13:47:15Z |

I would like to take advantage of the newest POWER8 cryptography enhancements - hardware and software.

Are there any white papers, articles, or summary pages available for our team to begin assessing what's possible with Linux?

  • Bill_Buros
    Bill_Buros
    169 Posts

    Re: Taking advantage of POWER8 crypto co-processors

    ‏2014-08-14T15:10:56Z  

    There are a number of things to look at and consider.

    Which compilers are being used?      IBM XL C/C++ has documented the Support for POWER8 processors

    The IBM Advance Toolchain for Power Linux supports and exploits the POWER features

    The latest IBM Java automatically exploits features on Power8.

    -Dcom.ibm.crypto.provider.doAESInHardware=true  option on IBM java7.1sr1 would automatically exploit the AES new instructions in P8.

    No program modification is needed.

    We are looking for additional and complementary documentation.

     

  • jhopper
    jhopper
    20 Posts

    Re: Taking advantage of POWER8 crypto co-processors

    ‏2014-08-14T15:39:15Z  

    Hi, if you are interested in the crypto co-processor (hardware accelerator) provided in POWER7+ and POWER8 servers, Kent Yoder has a whitepaper describing the driver and applications: https://www.ibm.com/developerworks/community/blogs/fe313521-2e95-46f2-817d-44a4f27eba32/entry/power7_accelerated_encryption_and_rng_for_linux22?lang=en

  • Bill_Buros
    Bill_Buros
    169 Posts

    Re: Taking advantage of POWER8 crypto co-processors

    ‏2014-08-14T15:44:25Z  

    Copied from one of the IBM Redbooks describing the IBM Power Systems S812L and S822L Technical Overview and Introduction.

     

    The POWER8 processor core is a 64-bit implementation of the IBM Power Instruction Set
    Architecture (ISA) Version 2.07 and has the following features:

    • Multi-threaded design, capable of up to eight-way simultaneous multithreading (SMT)
    • 32 KB, eight-way set-associative L1 instruction cache
    • 64 KB, eight-way set-associative L1 data cache
    • Enhanced prefetch, with instruction speculation awareness and data prefetch depth awareness
    • Enhanced branch prediction, using both local and global prediction tables with a selector table to choose the best predictor
    • Improved out-of-order execution
    • Two symmetric fixed-point execution units
    • Two symmetric load/store units and two load units, all four of which can also run simple fixed-point instructions
    • An integrated, multi-pipeline vector-scalar floating point unit for running both scalar and SIMD-type instructions, including the Vector Multimedia eXtension (VMX) instruction set and the improved Vector Scalar eXtension (VSX) instruction set, and capable of up to eight floating point operations per cycle (four double precision or eight single precision)
    • In-core Advanced Encryption Standard (AES) encryption capability
    • Hardware data prefetching with 16 independent data streams and software control
    • Hardware decimal floating point (DFP) capability.