I am trying to simulate a PowerPC 405 Multicore system with IBM PowerPC Multicore Instruction Set Simulator (version 2.04). RiscWatch (version 7.1.21) is used for debugging. For first tests, I just changed the smp example delivered with the simulator, that uses ppc470 cores, to use ppc405 cores instead. As there is no PIR register for the ppc405 I use a sprg register for that purpose.
The problem now is that synchronization between processors does not seem to work. Two processors can enter a critical region. The critical region is protected by lwarx/stwcx instructions. Caches are turned off.
Is it possible to simulate a multicore system with ppc405 cores and use lwarx/stwxc instructions to ensure mutual exclusion?
Is there anything specific that needs to be configured to get that working?
This topic has been locked.
1 reply Latest Post - 2013-01-19T11:41:12Z by SystemAdmin
Pinned topic PowerPC 405 Multicore synchronization problem
Answered question This question has been answered.
Unanswered question This question has not been answered yet.
Updated on 2013-01-19T11:41:12Z at 2013-01-19T11:41:12Z by SystemAdmin
SystemAdmin 110000D4XK277 Posts