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1 reply Latest Post - ‏2013-01-19T11:41:12Z by SystemAdmin
some_iss_user
some_iss_user
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Pinned topic PowerPC 405 Multicore synchronization problem

‏2012-02-13T14:45:54Z |
Hello,

I am trying to simulate a PowerPC 405 Multicore system with IBM PowerPC Multicore Instruction Set Simulator (version 2.04). RiscWatch (version 7.1.21) is used for debugging. For first tests, I just changed the smp example delivered with the simulator, that uses ppc470 cores, to use ppc405 cores instead. As there is no PIR register for the ppc405 I use a sprg register for that purpose.

The problem now is that synchronization between processors does not seem to work. Two processors can enter a critical region. The critical region is protected by lwarx/stwcx instructions. Caches are turned off.

Is it possible to simulate a multicore system with ppc405 cores and use lwarx/stwxc instructions to ensure mutual exclusion?
Is there anything specific that needs to be configured to get that working?

Thank you
Updated on 2013-01-19T11:41:12Z at 2013-01-19T11:41:12Z by SystemAdmin
  • SystemAdmin
    SystemAdmin
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    Re: PowerPC 405 Multicore synchronization problem

    ‏2013-01-19T11:41:12Z  in response to some_iss_user
    IBM PowerPC Multi-Core Instruction Set Simulator - how do you recompile the demo c code for ppc 440 after made some change (on Microsoft Windows XP platform).