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  • Latest Post - ‏2005-10-03T03:30:52Z by SystemAdmin
SystemAdmin
SystemAdmin
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Pinned topic Cell FlexIO Development Platform

‏2005-09-09T17:33:41Z |
A RamBus press release on the eve of ISSCC claimed RamBus memory and FlexIO technology accounted for 90% of cell pins. This includes 96 differential pairs of FlexIO processor busses.

In spite of this support for a connectionist model of parallel processing, the limited information available on IBM Cell blade prototypes suggests they may implement a dual symmetric multiprocessor model, presumably with shared memory. Can you confirm?

Do IBM Cell blade prototypes also support FlexIO bus connections to other cell processors?

Are there any other development platforms available that do support FlexIO bus connections to other cell processors?
Updated on 2005-10-03T03:30:52Z at 2005-10-03T03:30:52Z by SystemAdmin
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Cell FlexIO Development Platform

    ‏2005-09-11T20:51:21Z  
    The Cell Broadband Engine processor has a highly configurable I/O, physically 7 outbound Rambus FlexIO(TM)bytes (only 5 are used) and 5 inbound bytes. Logically the interface can be configured as two independent buses, one of which is an I/O bus, and the other can be either an I/O bus or a coherent bus. We are pretty flexible in how the bytes are allocated to either of these buses.
    Toshiba has published a paper (at Hot Chips) on a chip that interfaces to the IOIF, and IBM has announced support for custom systems (using the IOIF) through our Engineering and Technology Services organization.
    IBM has shown a prototype Cell blade, with two processors in a coherent configuration, with the coherent bus using 4 inbound and outbound bytes on each processor, and a remaining inbound and outbound byte pair on each processor going to a bridge chip.
    In the prototype Cell blade the FlexIO interfaces are used as internal interfaces to the blade only, and not exposed on the blade.
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Cell FlexIO Development Platform

    ‏2005-09-13T17:41:12Z  
    The Cell Broadband Engine processor has a highly configurable I/O, physically 7 outbound Rambus FlexIO(TM)bytes (only 5 are used) and 5 inbound bytes. Logically the interface can be configured as two independent buses, one of which is an I/O bus, and the other can be either an I/O bus or a coherent bus. We are pretty flexible in how the bytes are allocated to either of these buses.
    Toshiba has published a paper (at Hot Chips) on a chip that interfaces to the IOIF, and IBM has announced support for custom systems (using the IOIF) through our Engineering and Technology Services organization.
    IBM has shown a prototype Cell blade, with two processors in a coherent configuration, with the coherent bus using 4 inbound and outbound bytes on each processor, and a remaining inbound and outbound byte pair on each processor going to a bridge chip.
    In the prototype Cell blade the FlexIO interfaces are used as internal interfaces to the blade only, and not exposed on the blade.
    Thanks for your response, Peter. This seems to answer some of my questions and raises some new issues. Perhaps I'm being obtuse, or perhaps my queries were poorly framed. Let me try again.

    Are the Cell block diagrams I've seen accurate in their depiction of 96 differential pairs of FlexIO processor busses? Does this mean that, physically, there are 192 Cell signal pins dedicated to FlexIO processor busses?

    If so, given the range of FlexIO (about 15") and its intended use for intra-board connectivity, I don't see how I can use all of this connectivity - though the potential benefits are clear enough.

    The Toshiba IOIF prototype announced at Hot Chips may be the solution I'm seeking. Do you know if there are any production plans, perhaps by a member of the STI kieretsu?
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Cell FlexIO Development Platform

    ‏2005-09-14T17:30:05Z  
    Thanks for your response, Peter. This seems to answer some of my questions and raises some new issues. Perhaps I'm being obtuse, or perhaps my queries were poorly framed. Let me try again.

    Are the Cell block diagrams I've seen accurate in their depiction of 96 differential pairs of FlexIO processor busses? Does this mean that, physically, there are 192 Cell signal pins dedicated to FlexIO processor busses?

    If so, given the range of FlexIO (about 15") and its intended use for intra-board connectivity, I don't see how I can use all of this connectivity - though the potential benefits are clear enough.

    The Toshiba IOIF prototype announced at Hot Chips may be the solution I'm seeking. Do you know if there are any production plans, perhaps by a member of the STI kieretsu?
    Sorry, Peter, to paraphrase Mose Alison, my mind was on vacation and my mouth was working overtime. Thanks again for your response. I guess I had some misconceptions reinforced by ambiguous press reports.

    Toshiba describes their IOIF interface as a "Super Companion Chip" or SCC. It provides DDR2 memory, USB 2.0, Ultra ATA/133, PCI, PCI-X, gigabit ethernet, IEEE 1394 and video I/O interfaces in a 333 MHz, 1385 terminal PBGA.

    I'm interested in your thoughts regarding multiprocessor architectural designs with more than two Cell processors. Do you think designs will use PCI-X or gigabit ethernet? Can the unused outbound FlexIO bytes be used for external coherent bus selection? Are there interfaces or switches available to bridge FlexIO between circuit boards?
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Toshiba SSC

    ‏2005-09-15T14:43:07Z  
    Sorry, Peter, to paraphrase Mose Alison, my mind was on vacation and my mouth was working overtime. Thanks again for your response. I guess I had some misconceptions reinforced by ambiguous press reports.

    Toshiba describes their IOIF interface as a "Super Companion Chip" or SCC. It provides DDR2 memory, USB 2.0, Ultra ATA/133, PCI, PCI-X, gigabit ethernet, IEEE 1394 and video I/O interfaces in a 333 MHz, 1385 terminal PBGA.

    I'm interested in your thoughts regarding multiprocessor architectural designs with more than two Cell processors. Do you think designs will use PCI-X or gigabit ethernet? Can the unused outbound FlexIO bytes be used for external coherent bus selection? Are there interfaces or switches available to bridge FlexIO between circuit boards?
    WRT:

    >Toshiba describes their IOIF interface as a "Super Companion Chip"
    >or SCC. It provides DDR2 memory, USB 2.0, Ultra ATA/133, PCI, PCI-X,
    >gigabit ethernet, IEEE 1394 and video I/O interfaces in a 333 MHz, >1385 terminal PBGA.

    Ah ... this is a very important device/fact which I hadn't seen. Can you point me to anything public on this?

    In effect, this makes the IOIF into a FSB ... to what might be considered a combined northbridge/southbridge.. yes?

    Is memory-space simply address-partitioned ... between the XDR memory (if any?) and the DDR2 memory in the SSC?

    What are the bandwidth/latency values for memory transactions to the SSC?

    And I too would be interested in any discussion of larger-Nway interconnect schemes. Most of the applications i am interested in can tolerate fairly high interconnect latencies (they can run on today's beowolf clusters with Mellanox interconnects).
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Toshiba SSC

    ‏2005-09-15T16:57:39Z  
    WRT:

    >Toshiba describes their IOIF interface as a "Super Companion Chip"
    >or SCC. It provides DDR2 memory, USB 2.0, Ultra ATA/133, PCI, PCI-X,
    >gigabit ethernet, IEEE 1394 and video I/O interfaces in a 333 MHz, >1385 terminal PBGA.

    Ah ... this is a very important device/fact which I hadn't seen. Can you point me to anything public on this?

    In effect, this makes the IOIF into a FSB ... to what might be considered a combined northbridge/southbridge.. yes?

    Is memory-space simply address-partitioned ... between the XDR memory (if any?) and the DDR2 memory in the SSC?

    What are the bandwidth/latency values for memory transactions to the SSC?

    And I too would be interested in any discussion of larger-Nway interconnect schemes. Most of the applications i am interested in can tolerate fairly high interconnect latencies (they can run on today's beowolf clusters with Mellanox interconnects).
    The Toshiba Super Companion Chip, SCC, was first discussed in this thread by Peter Hofstee. Thanks again Peter. As he says, the SCC was introduced at the Hot Chips conference. I suggest you Google "Toshiba" and "Hot Chips."

    I can only speculate about the answers to your queries at this point, however the DDR2 memory likely buffers those device transactions supported on a 'best efforts' basis, USB 2.0, Ultra ATA/133, PCI, PCI-X and gigabit ethernet. The other devices are limited only by the capacity of the FlexIO bus.

    One of my interests is 'connectionist' architectures such as neural nets, where every node in a multi-layer network is connected to every node in the next layer. Assume a two dimensional array with m nodes per layer and n layers. The number of nodes is m*n, but the number of connections is m to the power of n. Hope I got that right.

    The closest approach to a connectionist architecture for Cell processors I can currently envision would use, for instance, a broadcast protocol with gigabit ethernet.

    Hope this helps.
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Toshiba SSC

    ‏2005-10-01T01:56:05Z  
    The Toshiba Super Companion Chip, SCC, was first discussed in this thread by Peter Hofstee. Thanks again Peter. As he says, the SCC was introduced at the Hot Chips conference. I suggest you Google "Toshiba" and "Hot Chips."

    I can only speculate about the answers to your queries at this point, however the DDR2 memory likely buffers those device transactions supported on a 'best efforts' basis, USB 2.0, Ultra ATA/133, PCI, PCI-X and gigabit ethernet. The other devices are limited only by the capacity of the FlexIO bus.

    One of my interests is 'connectionist' architectures such as neural nets, where every node in a multi-layer network is connected to every node in the next layer. Assume a two dimensional array with m nodes per layer and n layers. The number of nodes is m*n, but the number of connections is m to the power of n. Hope I got that right.

    The closest approach to a connectionist architecture for Cell processors I can currently envision would use, for instance, a broadcast protocol with gigabit ethernet.

    Hope this helps.
    Maybe an example will help:
    In the prototype blade we have shown the 5+5Bytes on each Cell BE chip are configured as two logical interfaces:
    • one coherent interface (4+4 of the 5+5 bytes) to the other Cell BE
    • one interface to a SouthBridge (1+1 of the 5+5 bytes) configured as an I/O interface

    We have designed the coherence protocol in such a way that a 4-way coherent system (4 Cell BE chips) is possible by using a switch chip (that we haven't built yet). The Cell BE is not designed to support larger than 4-way coherent systems.
    Because the IOIF/BIF interface is double non-standard (proprietary protocol and proprietary physical layer) we think it is not so easy to build systems on your own with Cell. Only Toshiba has disclosed a SouthBridge thus far. IBM provides support now for custom systems through engineering and technology services.
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Cell FlexIO Development Platform

    ‏2005-10-01T02:28:58Z  
    Sorry, Peter, to paraphrase Mose Alison, my mind was on vacation and my mouth was working overtime. Thanks again for your response. I guess I had some misconceptions reinforced by ambiguous press reports.

    Toshiba describes their IOIF interface as a "Super Companion Chip" or SCC. It provides DDR2 memory, USB 2.0, Ultra ATA/133, PCI, PCI-X, gigabit ethernet, IEEE 1394 and video I/O interfaces in a 333 MHz, 1385 terminal PBGA.

    I'm interested in your thoughts regarding multiprocessor architectural designs with more than two Cell processors. Do you think designs will use PCI-X or gigabit ethernet? Can the unused outbound FlexIO bytes be used for external coherent bus selection? Are there interfaces or switches available to bridge FlexIO between circuit boards?
    > Toshiba describes their IOIF interface as a "Super
    > Companion Chip" or SCC. It provides DDR2 memory, USB
    > 2.0, Ultra ATA/133, PCI, PCI-X, gigabit ethernet,
    > IEEE 1394 and video I/O interfaces in a 333 MHz, 1385
    > terminal PBGA.

    I believe that's PCIe (4 lane), not PCI-X.
    There's also audio I/O and a transport stream interface for digital TV tuner.
  • SystemAdmin
    SystemAdmin
    10114 Posts

    Re: Toshiba SSC

    ‏2005-10-03T03:30:52Z  
    Maybe an example will help:
    In the prototype blade we have shown the 5+5Bytes on each Cell BE chip are configured as two logical interfaces:
    • one coherent interface (4+4 of the 5+5 bytes) to the other Cell BE
    • one interface to a SouthBridge (1+1 of the 5+5 bytes) configured as an I/O interface

    We have designed the coherence protocol in such a way that a 4-way coherent system (4 Cell BE chips) is possible by using a switch chip (that we haven't built yet). The Cell BE is not designed to support larger than 4-way coherent systems.
    Because the IOIF/BIF interface is double non-standard (proprietary protocol and proprietary physical layer) we think it is not so easy to build systems on your own with Cell. Only Toshiba has disclosed a SouthBridge thus far. IBM provides support now for custom systems through engineering and technology services.
    >a 4-way coherent system... is possible by using a switch chip
    >(that we haven't built yet).

    What are your plans for a switch for 4-way coherent Cells?

    >Because the IOIF/BIF... is... nonstandard... we think it is
    >not so easy to build systems on your own with Cell.
    >Only Toshiba has disclosed a SouthBridge thus far.

    At 1385 pins, Toshiba's super companion chip provides 4 PCI slots, a PCI-X slot, USB, ATA, firewire, audio/video in/out and gigabit ethernet; when it ships in April 2006 with a power management IC as part of Toshiba's Cell reference set.

    IBM should consider licensing Toshiba's super companion and power management chips to standardize the Cell platform. Both IBM and Toshiba are RamBus XDR licensees.