z/VSE 6.2 Preview: Vector register support
Ingolf24 120000DRN3 Visits (8955)
In the following weeks I will post additional information of new functionality, we want to deliver with z/VSE 6.2 in the forth quarter 2017 - see my z/VS
Today I will start with the vector register support in z/VSE 6.2.
The IBM z13 / z13s processors introduces a new vector facility for z/Architecture (also called SIMD - single instruction, multiple data). A new set of vector instructions are available. They are described in the latest z/Architecture Principles of Operation (POP). These vector instructions work on up to 32 128-bit registers.
To minimize the required virtual storage for the vector register save area, z/VSE 6.2 provides a new VECTOR macro to activate and deactivate the vector support in an application (VSE task). If an activation request is successful, a vector register task save area is allocated in the 31 bit system GETVIS area. At deactivation this area is freed. The VSE interrupt handler stores the vector registers into that save area. When the task is dispatched again, those registers are restored.
Assembler applications, that exploit vector registers, may see good performance improvements.