Out of hiding - farley becomes Poulton...
orbist 060000HPM5 Comments (4) Visits (12686)
I am still alive.
I know I've been crap at posting for the last year or so, and really when it comes to it, I'm not going to say I'm sorry... for those of you that like sci-fi, and are of a certain age... those of you that watched Star-Trek Voyager when it first aired, will remember the half season that covered "the year of hell" - well it feels like we all woke up from something similar a few months ago... after the effort that was put in to get V7000 out the door last year... I'm glad our customers are reaping the benefits of all that effort... more of that to come soon
I was browsing things, and found the following on Nigels blog... I have to say I must disagree 100% and can refute every point (disclaimer, I know Nigel, like him, and I'm sure we shall discuss this in detail next time we meet!)
Here Nigel is talking about 3PAR, or should that be HP and even HDS in their wasted efforts in custom ASIC development.
1. It's been dead for the last 5-10 years. Its not going to last another 5. Writing 100 lines of Intel or Power assembler is MUCH more efficient than 3 years of custom silicon design,
2. Running at 3-4GHz with those 100 lines of assembler, is much more MIPS efficient especially when you use 64 bit offload instructions (SSE3,4 etc) than a custom ASIC running 1-2GHz
3. It is MASSIVELY dissimilar to VMware.
Any Virtual machine hypervisor system has a big job to do. Its got to do all the application work, and funnel all the I/O down through a few ports. Here, the bottleneck is the single physical machines access to the SAN. So offloading "data" blocks, i.e. sending a few SCSI level commands (with no data) using VAAI etc, means the server can do what the server needs to do, run its MIPS for applications, and save its SAN bandwidth for actual data.
Within a storage system, the kind of functions that 3PARs ASIC does can be "offloaded" to the CPU, i.e. Xeon or P6/7 CPU using its offload instructions, and no need for a custom (3 years later) ASIC.
The days of hardware offload ASICs in storage are already gone, I'd say completely the opposite of Nigel, if you didn't offload to the mainstream CPU 5 years ago, you are too late - forget the 5 years of ASICs... even EMC saw the light when Pepsi-MAX moved to Intel Xeons a few years ago (depsite their anti-SVC campaign against Intel in the SAN)
Sometimes you just have to admit that others are right, EMC did it with Pepsi-MAX, eventually HDS will give up on ASICs too, and then some time after that (if going by historical fact) HP too will realise the error in their ways and drag 3PAR with them....