Urban planning for chip process migration may indicate "up" instead of "out": In a recent thinkpiece, Solid State Technology magazine notes the growing trend of companies to plan for 3D integrated circuits and takes a look at what could be driving the move to 3D approaches using through-silicon vias (TSVs):
- Slow integration of low-k dielectric technology thanks to problems with mechanical failure, delamination, and other issues.
- Latency and processing speed for multicore processing (a difficulty which could be helped by shorter traces, TSVs, in the z-axis within bonded chip stacks).
- Hetero-integration (stacking a variety of chips requiring different processes).
- Form factor issues.
The article cites a report from chip manufacturers that discovered no difference in electrical performance between 32 and 22nm chips and postulated that to gain performance, it could be a lot cheaper to avoid changing to the 22nm-level litho and processes and just to stack the 32nm-feature processors. In fact, these techniques are already in use with memory chips (there is a face-to-face bonded processor and memory stack in the current PS3 so it can use 90nm chips to its best advantage instead of 65nm ones).