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On Games(SG14) and TM(SG5) from The View at the May 2015 C++ Standard meeting in Lenexa Community Blog
The yellow brick road starts here in Kansas (actually Lenexa) hosted by Perceptive Software, and it is called C++17. At this meeting, it lead with a major evening discussion on the philosophy of C++17 on a Monday night full session. This was motivated by...
from Blog: C/C++ compilers for IBM Z Blog
Modified on by Michael_Wong
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Transactional lock elision (TLE) can produce the effects of fine-grained locking and higher concurrency
KarenLawrence
Tags:
coarse-grained
lock
power8
elision
linux
tm
memory
power
parallel
htm
tle
ibm
fine-graned
aix
programming
optimize
transactional
18,255 Views
Transactional memory (TM) is a feature that was proposed some time ago in academia, but only recently has been implemented in modern, mainstream processors. TM is intended to simplify parallel programming, as an alternative to using locks. For example:...
from Blog: Power Systems IBM Redbooks
Modified on by ScottVetter
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Information on Demand 2013 - Register before September 13 to save Community Blog
Register before September 13, 2013 to save with the Early Bird Rate!! Join us in Las Vegas for a blend of business, technical and leadership training, along with the deep insights into Business Analytics, Enterprise Content Management and Information...
from Blog: IBM Innovation Center Canada
Modified on by GraceMBarker
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BoostCon 2010 Trip Report Community Blog
Hi, all. I came back from BoostCon2010: http://www.boostcon.com/program#schedule where I delivered three talks and participated in a panel discussion on Transactional Memory, along with such luminaries as Maurice Herlihy (the father of TM), Mark Moir (Sun),...
from Blog: C/C++ compilers for IBM Z Blog
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