With research, the CHREC is in the mail, autonomously
The National Science Foundation has started a new national center and consortium for fundamental research in reconfigurable computing. CHREC (the Center for High-Performance Reconfigurable Computing, pronounced "shreck") is two dozen academic, industry, and government organizations that share the goal of enabling reconfigurable computing; it will "go live" in January 2007. The goal of the center is to address the growing needs of high-performance and high-performance embedded computing (HPC and HPEC) by researching a relatively new concept in computing -- reconfigurable computing.
New reconfigurable computing technologies show promise by allowing users to maximize the existing hardware resources by providing system-aware software applications that can load balance and optimize the system, reconfiguring on the fly to achieve the most efficient operating state. This concept shows great promise in the areas of signal/image processing, cryptology, communications processing, data and text mining, optimization, and complex system simulations.
CHREC director Dr. Alan George explains the focus, goals, and implications of CHREC and its work:
On focus: Preliminary thrust areas for CHREC include device and core building blocks, reconfigurable systems and services, design automation and programming methods and tools, and reconfigurable and parallel algorithms and applications. Research projects in these areas are formulated on an annual basis in concert with Center partners, emphasizing a keen interest in exploring and evaluating new methods as well as key tradeoff analyses.
On main goals: A broad range of goals have been defined ... including
- Establish the nation's first multidisciplinary research center in reconfigurable high-performance computing as a basis for long-term partnership and collaboration amongst industry, academe, and government;
- Directly support the research needs of industry and government partners in a cost-effective manner with pooled, leveraged resources and maximized synergy;
- Enhance the educational experience for a diverse set of high-quality graduate and undergraduate students; and
- Advance the knowledge and technologies in this emerging field and ensure relevance of the research with rapid and effective technology transfer.
On impact: Although a relatively new field, reconfigurable computing has come to the forefront as an important processing paradigm for HPC, often in concert with conventional microprocessor-based computing. With RC, the full potential of underlying electronics in a system may be better realized in an adaptive manner. At the heart of RC, field-programmable hardware in its many forms has the potential to revolutionize the performance and efficiency of systems for HPC as well as deployable systems in high-performance embedded computing.
One ideal of the RC paradigm is to achieve the performance, scalability, power, and cooling advantages of the "Master of a trade," custom hardware, with the versatility, flexibility, and efficacy of the "Jack of all trades," a general-purpose processor.
As is commonplace with components for HPC, such as microprocessors, memory, networking, storage, etc., critical technologies for RC can also be leveraged from other IT markets to achieve a better performance-cost ratio, most notably the field-programmable gate array or FPGA. Each of these devices is inherently heterogeneous, being a predefined mixture of configurable logic cells and powerful, fixed resources.
Many opportunities and challenges exist in realizing the full potential of reconfigurable hardware for HPC. Among the opportunities offered by field-programmable hardware are a high degree of on-chip parallelism that can be mapped directly from dataflow characteristics of the application's defining parallel algorithm, user control over low-level resource definition and allocation, and user-defined data format and precision rendered efficiently in hardware.
There are many vertical challenges where we seek to bridge the semantic gap between the high level at which HPC applications are developed and the low level (i.e. HDL) at which hardware is typically defined. There are also many horizontal challenges where we seek to integrate or marry diverse resources such as microprocessors, FPGAs, and memory in optimal relationships, in essence bridging the paradigm gap between conventional and reconfigurable processing at various levels in the system and software architectures.
Success is expected to come from both revolutionary and evolutionary advances. For example, at one end of the spectrum, internal design strategies of field-programmable devices need to be re-evaluated in light of a broad range of HPC and HPEC applications, not only to potentially achieve a more effective mixture of on-chip fixed resources alongside reconfigurable logic blocks, but also as a prime target for higher-level programming and translation. At the other end of the spectrum, new concepts and tools are needed to analyze the algorithmic basis of applications under study (that is, inherent control-flow versus data-flow components, numeric format versus dynamic range), and new programming models to render this basis in an abstracted design strategy so as to potentially target and exploit a combination of resources (that is, general-purpose processors, reconfigurable processors, and special-purpose processors such as GPUs, DSPs, and NPs).
One of the inherent advantages of RC is that it promises to support these goals [cost of building highly heterogeneous systems form diverse catagories and achieving uni-paradigm app design for multi-paradigm computing] in a more flexible and cost-effective manner. Between the two extremes of devices and programming models for multi-paradigm computing, many challenges await with new concepts and tools -– compilers, core libraries, system services, debug and performance analysis tools, etc. These and related steps will be of paramount importance for the transition of RC technologies into the mainstream of HPC.
Partners (so far) in CHREC includeAir Force Research LaboratoryArctic Region Supercomputing CenterGeorge Washington UniversityHewlett-PackardHoneywell AerospaceIBM ResearchIntelNASA Goddard Space Flight CenterNASA Marshall Space Flight CenterNational Cancer InstituteNational Security AgencyOak Ridge National LaboratoryOffice of Naval ResearchRockwell CollinsSandia National LaboratoriesSilicon GraphicsSmiths AerospaceUniversity of Florida
with several other members pending.