December 10, 2019 | Written by: Huiming Bu and Veeraraghavan Basker
Categorized: AI Hardware
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Over the last five decades, semiconductor technology has been the engine for computing hardware. And in the last ten years, FinFET architecture has gradually dominated the semiconductor market. This technology continues to scale with ever-demanding requirements in density, power and performance, but not fast enough: innovations are still needed to meet the demand for faster, more powerful AI hardware.
IBM Research has been working on GAA transistors for more than a decade and the device architecture has evolved from single nanowire to stacked nanosheet. In 2015, researchers published the first nanosheet paper at S3S conference, naming “nanosheet” for the first time. IBM Research continues to work closely with partners to accelerate the industry transition from FinFETs to nanosheet transistors.
Technology evolution from FinFET to NanoSheet device architecture for 5 nm and beyond
At this year’s IEEE International Electron Devices Meeting (IEDM, Dec 7-11th, 2019), the top conference for semiconductor device technology, IBM Research is presenting the latest progress in nanosheet technology, including new critical features for high performance computing. In a new computing era driven by AI and 5G, nanosheet’s technology features make it a superior device architecture for both mobile and HPC products.
IBM Research’s superior device architecture utilizes Gate-All-Around (GAA) stacked nanosheets, which address several challenges incumbent to FinFETs for the true 5 nanometer (nm) node and beyond.
- More computing performance and less power consumption: NanoSheet provides a better power-performance design point due to better electrostatic control in GAA and higher footprint density. Compared to the latest and greatest 7nm FinFET technology now available in the foundry, NanoSheet technology offers more than 25 percent performance enhancement at the same power, or more than 50 percent power saving at the same performance.
- Variable sheet width with more streamlined design: It is worth noting Nanosheet technology is a better device architecture for computer products in the age of AI and 5G due to its variable sheet width enabled by Extreme Ultraviolet Lithography (EUV). This allows for a far more versatile device design, as nanosheet devices with different channel widths can be co-integrated in the same chip for futher power-performance optimization.
- Channel Thickness control: Growing the NanoSheet stack’s channel layers can create an atomic-level control for channel formation. Such precise channel thickness control is not possible for FinFETs as it is defined by lithography in conjunction with RIE, where local and global process variations are much higher than the epitaxial thickness variation.
The following IBM Research papers at IEDM share more about the latest advances in nanosheet technology:
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
Presented by IBM Researcher Jingyun Zhang
Due to its superior electrostatics, a nanosheet Gate-All-Around (GAA) device can enable extremely scaled gate lengths (Lmet). Along with wide sheets, Lmet scaling is crucial to meet high performance computing needs. To obtain good short channel behavior for such extremely scaled Lmet, controlling sub-fin leakage is critical. In this paper, researchers developed a full Bottom Dielectric Isolation (BDI) scheme by inserting a dielectric layer underneath both the S/D and gate regions that eliminates sub-channel leakage for scaled Lmet. In addition, this feature reduces parasitic capacitance and provides additional power-performance improvement for GAA nanosheet technology.
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
Presented by IBM Researcher Ruqiang Bao
In a GAA nanosheet channel structure, the gate region has evolved to 4D due to the presence of sheet-to-sheet spacing (Tsus). Controlling the Tsus thickness while meeting the multiple threshold voltage requirements is fundamental to meeting the HPC needs. IBM Researchers have invented novel processes and an integration scheme to implement multiple dipole thicknesses to achieve multi-Vt without volume occupation (i.e., volumeless multi-Vt) to enable very thin Tsus. Additionally, researchers have invented a process to control the metal gate boundary during patterning in wide sheets, solving a fundamental issue in nanosheet technology.
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around Nanosheet Devices
Presented by IBM Researcher Nicolas Loubet
A unique structural feature for GAA nanosheet technology is the formation of an Inner Spacer in the device architecture. We have developed a novel isotropic dry etch technique to precisely control the lateral silicon germanium etch with very high selectivity to silicon (>150:1) and dielectrics (>1000:1). Additionally, this superior etch process can be used during the channel release process, delivering very low channel thickness variability with electrostatics and resistance variation, which is critical for power/performance optimization of high-performance computing stacked nanosheet devices.
1. “5 nanometer transistors inching their way into chips,” Huiming Bu, https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/
2. “Samsung Electronics’ Leadership in Advanced Foundry Technology Showcased with Latest Silicon Innovations and Ecosystem Platform,” https://news.samsung.com/global/samsung-electronics-leadership-in-advanced-foundry-technology-showcased-with-latest-silicon-innovations-and-ecosystem-platform
3. “IBM Shows The World How To Build A Super Dense 5-Nanometer Chip,” Forbes, Jun 5, 2017 https://www.forbes.com/sites/aarontilley/2017/06/05/ibm-5nm-chips/#4292d8873c56