Extreme ultraviolet (EUV) lithography is finally here. How far will it go?

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In late 2017, IBM successfully launched the next era of high-performance cognitive and AI hardware with the deployment of its POWER9 technology in the Summit and Sierra supercomputers, the most powerful supercomputers in the world to date.  Not to be outdone, IBM also launched the next era of constant-encryption mainframes, with the popular release of the new z14 enterprise mainframe for the new digital economy.

These twin advancements in computing hardware rely on 14nm logic technology developed at IBM Research earlier this decade. IBM has also reported on a pipeline of semiconductor technology-anchored innovations for exponential acceleration of AI computations. This underscores how advanced research and development in silicon technology still drives advancements in modern computing, and why IBM continues to push the boundaries of advanced logic nodes.  For both the 7nm and 5nm nodes, IBM and its alliance partners at the SUNY Poly Colleges of Nanoscale Science and Engineering in Albany, NY relied heavily on transistor and interconnect patterning driven by Extreme Ultraviolet (EUV) lithography. Since these, and future, nodes will drive the next advancements in cognitive and mainframe hardware, it is imperative that the semiconductor industry understand how far (and how small!) EUV technology can be extended.


IBM researchers Anuja De Silva, Luciana Meli and Jing Guo (from left) who are presenting at SPIE

IBM and its development partners are fully committed to extending EUV patterning technology to its limits, and five papers at this week’s 2018 International Society for Optics and Photonics (SPIE) Advanced Lithography conference will show how much the technology can be extended to the 5nm, 3nm, and future nodes.  To extend EUV patterning, all aspects of equipment, materials, and process must be explored to their limit.

This exploration starts with the fundamental variability of ASML’s EUV lithography system, with which IBM now has four years of experience.  In the paper “Characterization and control of EUV scanner dose uniformity and stability,” Chris Robinson fully characterizes the exposure stability of a pre-manufacturing EUV system and shows that although its exposure control is far from perfect, proper characterization and control techniques can improve performance.

Extending EUV lithography to its fullest potential will require revisiting some of the oldest assumptions of the lithography process itself. In the paper “Aqueous developers for ultrathin chemically amplified EUV resists,” Dario Goldfarb dives into the fundamental physical and chemical process of lithography to show potential new pathways forward to high-contrast imaging.  In this manner, he opens the proverbial “black box” of the lithography development process and thus gives new life to current patterning materials to extend beyond the 5nm node.

Further frontiers in patterning will depend on advancements in patterning materials, and two talks, “Polymer brush as adhesion promoter for EUV patterning” by Jing Guo and “Silicon-based hardmask development for EUV patterning” by Anuja De Silva, add vital tools to the patterning toolbox.  Both of these talks highlight the results of years of materials innovation in patterning films by IBM engineers, as well as deep collaborative efforts with many critical vendors in the semiconductor industry.  The results of this intense invention, characterization, and collaboration fully enable EUV patterning at the dimensions necessary for the 5nm and 3nm nodes.

Achieving patterning yields that are compatible with bleeding-edge logic manufacturing is a complex feat. Luciana Meli, in “Defect detection strategies and process partitioning for single expose EUV patterning,” ties together many of the concepts discussed above to show how to measure, understand, and improve upon the factors that drive semiconductor process yield at dimensions that are no wider than a few stands of DNA, with perfection over a 12-inch wafer.

By continuing to push the boundaries of advanced logic nodes, IBM and its partners continue to drive the semiconductor roadmap ahead for the next decade. It’s imperative that we continue innovating in this new era of chips and systems designed specifically for exponential improvements in AI workloads.

All IBM presentations at SPIE Advanced Lithography 2018:

  • Anuja De Silva – Inorganic Hardmask Development for EUV Patterning
  • Charlie Liu – The integration of 193i and DSA for BEOL metal cuts/blocks targeting sub-20nm tip-to-tip CD
  • Chris Robinson – Characterization and Control of EUV Scanner Dose Uniformity and Stability
  • Dario Goldfarb – Aqueous Developers for Positive Tone Ultrathin EUV Resists
  • Dexin Kong – In-line Characterization of Non-Selective SiG Nodule Defects with Scatterometry Enabled by Machine Learning
  • Jing Guo – Polymer brush as adhesion promoter for EUV patterning
  • Luciana Meli – Defect detection strategies and process partitioning for SE EUV patterning
  • Nelson Felix – Exploring the limits of 0.33NA EUV application at IBM Research
  • Raja Muthinti – Novel Hybrid Metrology for process integration of Gate all around (GAA) devices


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