This article authored by Myung-hee Na, Senior Technical Staff Member, Semiconductor Technology Research, IBM Research; Karim El Sayed, Director of R&D, Synopsys; Victor Moroz, Synopsys Fellow, Synopsys
The number of variables in semiconductor development seem to be inversely proportional to a chip’s dimensions – the smaller our chips get, the more complicated they are to build.
In the past, the development of new semiconductor technologies was focused on the scaling and optimization of a single device architecture, the planar MOSFET (transistors used up to 22nm), and a single material, silicon. But today and into the future, complexity will only accelerate because of the need to evaluate and select among a larger number of processes, device architectures and materials in order to meet the power, performance, and other targets expected by the market. This means that today the number of potential pitfalls almost matches the number transistors on a chip!
That’s why IBM Research and Synopsys have entered into a joint development agreement (JDA) to develop new state-of-the-art Electronic Design Automation (EDA) flows. Our goal: use software to holistically automate the method, evaluation, and assessment – the flow – of the elements that go into today’s latest transistors, like our 3D FINFET 7nm chip, and beyond.
We’ll be able to know about, and act upon nano-scale variables in design, materials, and processing techniques across a chip’s entire design – preventing costly errors, while optimizing which technology path to pursue. And all of this analysis will be done before a single wafer is made.
Synposys’s tools cover the entire range of EDA, from high level architectural design, through synthesis, physical design and manufacturing. It is this breadth of EDA tools, including those used for semiconductor technology development and manufacturing, that make it a perfect match for IBM’s device and process technologies expertise.
In the not too distant past, once process engineers verified that a technology worked with good yield, they would “toss it over the wall” to manufacturing. Designers would then start working with the new process design kits to design integrated circuit products. But as scaling progressed, and process technology become more complex, engineers and designers realized that this sequential process wasn’t going to work. For example, process groups would miss important design-level criteria which would impact performance or yield. This gave birth to the idea of feeding design information back into technology development.
Getting the holistic picture
The move to FinFET, and the exploration of new materials means that the communication between design and technology development is critical, but there isn’t enough time or investment to evaluate all the options. This is where the new EDA flow helps: we can evaluate the technology options holistically, taking into account design criteria upfront, in the software, “virtually,” saving time and money.
Combining design with technology development, and starting before wafers are even available, will improve the performance and quality of the chip products designed on the technology as well as speed up the time it takes to deliver them.
We expect that the new EDA flows will make an impact in the development of 7nm and beyond technology node.
For IBM’s part, it also wants other partners to use these flows and the process design kits (PDK) for our technologies developed with these flows. By making these PDKs available to our partners early in the development process we can save time in ramping up a new technology into production.
More specifically, this collaboration will further enhance Design-Technology Co-Optimization (DTCO) efforts under way within the IBM-Samsung-GLOBALFOUNDRIES Pathfinding semiconductor scaling project, developing highly automated EDA methodologies to enable industry leading turn-around time. Furthermore, we hope to influence the broader semiconductor industry by introducing comprehensive EDA flows for technology innovation with novel design that delivers deeply scaled technologies.