Having lower power implementation, this optical receiver provides a new paradigm to interconnect technology and has the potential to replace 56 Gb/s copper interconnects. In addition, a matching optical transmitter is expected to follow sometime next year. The two devices will complement each other to form a complete optical-receiver built in CMOS (Complementary metal-oxide-semiconductor) and promise to be more cost efficient than the standard copper interconnects.
IBM electrical engineer, Alessandro Cevrero, tells us more about the development of this low-cost optical receiver in this short interview.
So, what are you developing exactly?
Alessandro Cevrero (AC): To be exact, we’re developing a single lane 60-Gigabit per second optical receiver with non-return to zero (NRZ) signaling, targeting low cost multi-mode vertical-cavity surface-emitting laser (VCSEL) based links. Designed in 14-nanometer CMOS finFET (fin field-effect transistor), the receiver features low power implementation with high jitter tolerance enabled by digital clock and data recovery.
Can you explain in a nutshell what this new technology means?
(AC): Basically, we’ll be able to replace electrical links in the short interconnect from processor-to-processor, processor-to-memory, from drawer-to-drawer inside a rack and from a rack to a tier-1 switch within a data-center.
What’s the advantage in that?
(AC): Actually, it’s quite revolutionary because from now on all the interconnects above 1m will be eventually converted from electrical to optical, which is not only more energy efficient, it also provides much more bandwidth. Unlike optical links, electrical links require complex equalization for high data volumes and hence, consume more power. Our technology beats the competition as its power usage is way lower – 120 milliwatts (mW) for the receiver and eventually 300 milliwatts (mW) for the full transceiver. What’s more, the cable length for our optical solution spans up to 100 meters – a huge difference to the limited two meters electrical links offer.
Can you explain the function of the CMOS die?
(AC): Implementing the entire 60 Gb/s receiver on a small CMOS die, doubles the transmission speed, essentially cutting the cost per Gigabit per second in half. Basically, our work demonstrates that a CMOS can achieve good optical sensitivity at data rates above 32 Gb/s at much lower power consumption than a SiGe solution, for example. This breakthrough CMOS photonics technology allows for closer proximity to the processor or switch chip, which provides superior sensitivity (-9 decibel-milliwatts), enables high bandwidth connectivity and is ideal for the high throughput requirements of cloud computing.
How difficult is it to pull this off? Any major challenges?
(AC): As the signal to the receiver is rather weak, the biggest challenge is to amplify the signal without corrupting the information. To pull this off, we need to make sure that we can transfer data reliably. This requires achieving a bit error rate (BER) of 10 -12, which essentially means that when transmitting 1012 bits, only one could be incorrect. At this level, we would be able to deploy our receivers in a real data center.
What are the next steps for your research?
(AC): We are currently working on a prototype targeting above 70Gb/s. We’ve also already manufactured an optical transmitter, for which measurements are expected to start in the fourth quarter of this year.
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Ten months ago we assembled a team from IBM Research in Switzerland and IBM tape developers based in Tucson, Arizona, to try to build something which has never been built before to address a risk that may not materialize for another decade or more. As you can tell, we love a good challenge.