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Carbon nanotubes (CNT) appeal to the semiconductor industry because they’re superior electrical conductors compared to silicon with a mere 1 nanometer body thickness. So why don’t we have CNT chips in everything from mainframes to mobile devices, yet? Scalability of the transistor and large-scale integration are still big challenges. But two papers my colleagues and I recently published in Science and Nature Nanotechnology show promising breakthroughs in these two areas critical to CNT chip reality.
Footprint achievement tips the nanoscale
First: scaling. We know 3D FinFET silicon chips could hit their power and performance limit at 7 nanometers. And while the recent announcement of 5nm silicon nanosheet transistors boost scale, power, and performance at the next node, we know its limits, too.
A transistor is more than its gate. The Source, Drain, and spacers all add up for a total footprint. Pictured: a CNT transistor with a 40nm footprint. (Figure 1B in “Carbon nanotube transistors scaled to a 40-nanometer footprint”, published in Science.)
In our Science paper “Carbon nanotube transistors scaled to a 40-nanometer footprint,” we scaled an entire CNT transistor to The International Technology Roadmap for Semiconductors’ (ITRS) goal of transistors reaching a 40nm footprint – a goal they set and haven’t changed since 2015. For reference, today’s top-of-the-line 14nm transistors actually take up about 90nm of chip real estate.
We can potentially scale a CNT transistor further than silicon for the primary reason that they’re intrinsically only 1.2 nm thick. This thinness has the domino effect of reducing gate length to 10 nm because it provides a better electrostatic control of the gate, and helps minimize current leakage. Plus, electrons travel faster in CNTs than silicon, enhancing device performance.
But we needed a new way to connect CNTs to their source and drain (pictured). We had to find the perfect mix of materials that could “bake” these 10nm elements together at a manufacturable temperature. Our previous working end-bonded contacts between source-and-CNT, and drain-and-CNT required processing temperatures so high, at around 850°C, that the channel could not be any shorter than 60–100 nm. Switching to a cobalt-molybdenum alloy for the wiring between the elements effectively lowered the temperature to an acceptable 650°C – shrinking the distances down to 10nm.
Dr. Qing Cao, the lead author of the paper, and other colleagues on the team demonstrated that – at this newly achieved footprint – the CNT transistor can achieve performance at a level comparable to today’s transistor standards.
CNT elements come together on ring oscillator
Demonstrating such an extremely scaled single transistor, even with a less manufacturable process flow, gave us the motivation to solve the integration challenges for practical CNT technologies. And for the last five years, my team has been developing individual elements of CNT technology. We know how to separate semiconducting CNTs, make CNTs “self-assemble” on a wafer, and fabricate reliable n-channel CNT Field Effect Transistors, or “FETs” (which usually degrade quickly due to contact metal oxidation) using various techniques.
All elements have to work simultaneously in a functional ring oscillator. Pictured: Top-view scanning electron microscopy image of a 5-stage CNT ring oscillator and CNTs placed trenches. (Figure 1B in “High-speed logic integrated circuits with solution processed self-assembled carbon nanotubes”, published in Nature Nanotechnology.)
The challenge in developing a disruptive, early-stage technology is that some techniques used to solve one issue can end up destroying other elements of the device and the circuit. This is the fundamental reason why all nanotechnology-based demonstrations, like those using CNTs, were limited to a very low integration level. And it casts doubt on the feasibility of using them in a practical way.
But we took a major step forward in solving this integration challenge in our Nature Nanotechnology paper, “High-speed logic integrated circuits with solution processed self-assembled carbon nanotubes,” where we show how to put all the pieces together to make a standard benchmark circuit in any logic technology – a CMOS ring oscillator.
Dr. Jianshi Tang and my other team members combined our previously developed methods to purify and place CNTs together (individually, they look like penne pasta floating in solution), but made one key adjustment by adding a sidewall oxide to protect the n-FET channel from degrading during the manufacturing process (the sidewall resulted in a three times higher yield, further ensuring that the requirement of all elements on the ring oscillator work simultaneously is met).
The functional 5-stage CMOS ring oscillators described in the paper (and pictured, above) can already work at 1 V (an industry standard). Despite low CNT density in the channel (you can see the six CNTs in the same picture) and relaxed parameters, the stage switching frequency reaches 2.8 GHz (355 picosecond) – the first example of breaking the GHz barrier for any nanotech based demonstrations. It is projected that, with a density of more than 100 CNTs per micrometer, and properly scaled device dimensions, we can achieve sub-picosecond stage delay, significantly faster than today’s silicon chips.
As we write in the paper:
Since CMOS ring oscillators directly reflect the maturity of the technology, it is long-awaited proof that the important issues of transitioning this promising material into a real technology are being vigorously resolved.