When we announced the industry’s first functional 7 nanometer node (7nm) test chips in 2015, with our GLOBALFOUNDRIES and Samsung partners, we knew the process for the chips to reach “manufacturing maturity” – perhaps as early as next year, would be rapid. As that effort accelerates in the semiconductor industry, IBM continues to push the boundary by focusing on the challenges of the next nodes beyond 7nm.
Our IBM team is presenting seven papers at this week’s 2017 International Society for Optics and Photonics (SPIE) Advanced Lithography conference focused on technology exploration and enablement beyond the 7nm node. And it starts with Extreme Ultraviolet (EUV) Lithography.
With 7nm chips, we’re now creating designs relating to a transistor’s size, or even the wiring between transistors, that are truly at the atomic level. To achieve this kind of scaling without overly-complex patterning schemes, EUV is key. In a single exposure, EUV can create a high-resolution pattern that is unattainable by prior semiconductor patterning processes. However, enabling EUV patterning requires specialized equipment, process, and know-how, all found at IBM’s research labs in Albany, NY and Yorktown Heights, NY. These seven advances presented at SPIE relating to EUV masks (templates used to print circuit designs onto a silicon wafer), and patterning materials (light-activated “resists” or etch-resistant materials), can all be seen as critical in enabling 7nm technology and beyond:
In Design intent optimization at the beyond 7nm node: The intersection of DTCO and EUVL stochastic mitigation techniques, Michael Crouse shows that even though the title of his talk is big, small changes in wiring designs can drastically improve printing conditions. In Figure 1, he shows that if the optimization of mask shapes is done correctly, continuous lines without breakage can be printed at the smallest dimensions required for the 7nm node and beyond.
In Investigation of alternate mask stacks in EUV lithography, Martin Burkhardt simulates the performance of new materials not being used currently for EUV masks. By considering the whole periodic table, he is able to illustrate that EUV masks which provide even better contrast are within our grasp. Actually fabricating masks with some of these materials would allow for higher fidelity patterns on a silicon wafer without any further change in EUV technology, and thus allow the industry to scale easily beyond 7nm.
In Comprehensive analysis of line-edge and line-width roughness for EUV lithography, Ravi Bonam illustrates how small imperfections and wiggles in a wiring line can be characterized clearly, and in doing so shows which conditions produce the straightest features, critical for improving manufacturability of the EUV patterning process, and the performance and yield of the chip.
In Fundamentals of EUV resist-inorganic hardmask interactions, Dario Goldfarb looks to improve the patterning material film stack (the point of transfer from pattern to wafer) by improving the physical and chemical interactions at the interfaces between these films, which often don’t like to stick to each other. He harnesses this understanding to create specific chemical interactions to hold these materials together (shown in Figure 2), which is critical to ensuring these tiny, EUV-patterned shapes are able to stay in place long enough to transfer their patterns into the substrate below.
In a similar theme to Dario Goldfarb’s talk, Indira Seshadri demonstrates in Ultrathin EUV patterning stack using polymer brush as an adhesion promotion layer, that by employing a polymer-like material that bridges between tiny EUV-patterned features and the underlying substrate, these very high-resolution patterns can be etched into the substrate below and retain the intended design shape, key to ensuring yieldable chips at these length scales.
With so many new thin-film solutions in play, the ability to discern and improve manufacturing-worthy processes early in the research phases is key. In a talk entitled “Driving down defect density in composite EUV patterning film stacks”, Luciana Meli demonstrates systematic case studies, using a hybrid of available defect inspection techniques, to show the process and materials improvements necessary to deliver the low defectivity required for 7nm and beyond EUV manufacturability.
Bringing many of these concepts of imaging and materials improvements together, Anuja De Silva will present a talk entitled “Single-expose patterning development for EUV lithography”, showcasing successful patterning of wiring circuits at the dimensions of 30nm and below required beyond the 7nm node. The ability to achieve this represents a large leap from the capabilities first available for the 7nm node (see Figure 3), and can actually improve the 7nm node itself, though she will highlight the challenges that still remain to enable fully functioning, yieldable chips at dimensions required for technology beyond 7nm.
A 7nm chip has 20 billion transistors in the space roughly the size of a fingernail. They’ll make their way into systems and devices, extending the capabilities – and Moore’s Law – to do ever-more demanding tasks in data analysis, cognitive computing, and whatever the next generation of mobile apps hold. The work presented at SPIE this year nudges the industry closer to patterning solutions that not only make the 7nm process more robust with single-expose EUV, they also enable further scaling to realize even more power/performance benefit for years to come.
Other IBM Presentations at 2017 SPIE
Decomposition of the TCC using non-coherent kernels for faster calculation of lithographic images, Alan Rosenbluth
Development of Ti containing hardmasks through PEALD deposition, Anuja De Silva
DSA patterning options for logics and memory applications, Charlie Liu
Electrical study of DSA shrink process and CD rectification effect at sub-60nm using EUV test vehicle, Cheng Chi
Reaching for the True Overlay in Advanced Nodes, Chiew-Seng Koay
Topcoat-free Strategies for Orientation Control of All-organic High-χBlock Copolymers, Dan Sanders
Identification and reliability sensitivity analysis of a correlated ground rule system (design arc), Eric Eastman
Advanced fast 3D DSA model development and calibration for design technology co-optimization, Kafai Lai
Unexpected Impacts of RIE Gases onto Lithographic Films, Martin Glodde
Electrical Test Prediction using Hybrid Metrology and Machine Learning, Mary Breton
Reducing LER in Si and SiN Through RIE Optimization for Photonic Waveguide Applications, Nathan Marchack
Directed Self-Assembly Patterning Strategies for Phase Change Memory Applications, R. Bruce
Materials characterization for process integration of multi-channel gate all around (GAA) devices, Raja Muthinti
Comprehensive analysis of line-edge and line-width roughness for EUV lithography, Ravi Bonam