Another kind of chip with carbon nanotubes

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This is the second of a four-part series about IBM featured papers at IEDM 2016.

The annual International Electron Devices Meeting is “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” So IBM researchers brought their scanning probe thermometer, their air spacer for a 10 nanometer chip, their 7 nm chip, and not to be out-done by silicon, they brought their carbon nanotubes, too. These papers and presentations by IBMers and many partners will take part in this week’s conference in San Francisco.

IEDM features four IBM papers as some of the conference’s best examples of this re-imagining of computing — extending Moore’s Law, and building new architectures, and using new materials to go beyond it. Here is a closer look at these papers, and the scientists behind the work. This part of the series examines the paper “Carbon Nanotube Complementary Logic with Low-Temperature Processed End-Bonded Metal Contacts”, by IBM research scientist and post-doc Jianshi Tang.

Even with the advancement of 10, 7, and possibly even 5nm chips, the industry knows, and is preparing itself for life after silicon. Carbon nanotubes (CNTs) hold promise as the next material for the next generation of computers. CNTs are 1 nm wide tubes of pure carbon that are superior to silicon in conducting electricity while consuming less energy. The challenge for such small transistors is to maintain good electrical contacts with the CNTs when their contact area becomes so extremely small.

IBM’s Manager of Nanoscale Science and Technology Shu-Jen Han and his team at the Thomas J Watson Research Center have developed a new way to connect CNTs to a wire made of metals in which carbon atoms can easily dissolve (breaking the C-C bonds to make it possible to build the contact). This new approach, which Tang, a member of Han’s team, will present at IEDM, can significantly lower the required temperature to form single-point, end-bonded contacts to CNTs – a significant improvement compared to the team’s previous demonstration, last year. The team’s ability to successfully lower the contact-bonding temperature from 900 C, to between 400 and 600 C is within a manufacturable range.

At left is a schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts. The graph at right shows the Ids-Vgs curves of the PFET and NFET in one CNT inverter.

Left: a schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts. Right: The graph shows the Ids-Vgs curves of the PFET and NFET in one CNT inverter.

Tang will also discuss how the team accomplished another CNT first: the first n-type end-bonded contacts. Up until now, only p-type end bonding was possible. N-type and p-type transistors describe the flow of charges – negatively (discharge the circuit stage), and positively (charge the circuit stage) – within a chip. This complimentary flow of charges between transistors is essential for today’s semiconductors, and key to building a working CNT chip – and now much closer to reality.

Han also sees intermediate uses for CNTs, such as sensors and flexible electronics. Unlike rigid silicon, CNTs can be deposited anywhere, creating IoT-enabled wearables. CNTs’ sensitivity to environmental changes could also be harnessed to monitor air quality or detect biomarkers for early disease diagnosis.

Read part one: Mapping hot spots

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