Posted in: Microelectronics, Nanotechnology, Systems

Air spacers for 10nm chips

This is the third of a four-part series about IBM featured papers at IEDM 2016.

The annual International Electron Devices Meeting is “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” So IBM researchers brought their scanning probe thermometer, their air spacer for a 10 nanometer chip, their 7 nm chip, and not to be out-done by silicon, they brought their carbon nanotubes, too. These papers and presentations by IBMers and many partners will take part in this week’s conference in San Francisco.

IEDM features four IBM papers as some of the conference’s best examples of this re-imagining of computing — extending Moore’s Law, and building new architectures, and using new materials to go beyond it. Here is a closer look at these papers, and the scientists behind the work. Part three is about the paper “Air Spacer for 10nm FinFET CMOS and Beyond”, by Dr. Kangguo Cheng, a senior technical staff member and Master Inventor at IBM Research.

While 14 nm node chips can be manufactured today, significant challenges remain in making the leap to the next node. As transistors get smaller, the parasitic capacitance (unwanted electrical charge) causes two issues: the signal switching between transistors slows down, while power consumption increases. Cheng and his team at IBM’s Albany Nanotech Center explored how to use air as an insulator in 10 nm transistors. Their air spacers have shown to reduce capacitance at the transistor level by as much as 25 percent, and reduced capacitance in a ring oscillator test circuit by as much as 15 percent.

A transistor has four essential elements: a channel, two reservoirs (so-called source and drain) at two ends of the channel, and a gate controlling the channel to turn the transistor on or off. Contacts (metal alloys) are used to connect source, drain, and gate to the wires above the transistors that then connect to complete the rest of the circuit. As transistors get smaller and smaller, as well as closer and closer together, so do the gaps between a transistor’s contacts. Some of the electrical charge, instead of flowing into the channel to do useful work, gets stored in these gaps. When the transistor switches, the stored charge comes out again, wasting energy. As more power is needed to move these additional electrons back and forth, more energy is needed to make the chip work – which also makes it hotter, sometimes to the point of being unusable.

Top left: TEM image of a FinFET transistor with air spacers (the white spaces) at 10nm dimensions. Top right: Damage after an aggressive spacer pulldown process; specifically, erosion of the fin and source/drain epitaxy. Below the images: Schematic of a partial air spacer structure. Air spacers are formed only above the fin top to minimize the impact on the gate stack. Dielectric liners are used to further protect gate stacks during air spacer fabrication processes.

Top left: TEM image of a FinFET transistor with air spacers (the white spaces) at 10nm dimensions. Top right: Damage after an aggressive spacer pulldown process; specifically, erosion of the fin and source/drain epitaxy. Bottom middle: Schematic of a partial air spacer structure. Air spacers are formed only above the fin top to minimize the impact on the gate stack. Dielectric liners are used to further protect gate stacks during air spacer fabrication processes.

So, a new material was needed to put between nearby contacts to help prevent those pesky electrons from sticking between the contacts. It turns out that the best material is no material at all — it’s air. So the IBM team worked to figure out how to create a tiny space filled with air between the transistor’s contacts to help control how many electrons get stored in the gaps. The process developed results in transistors that use 25 percent less power, and by extension, 15 percent less power for the entire circuit.

Air spacers will help to reach 10 and 7 nm chips, as well as potentially more-efficient 14 nm chips, for next-generation systems.

Read part one: Mapping hot spots
Read part two: Another kind of chip with carbon nanotubes

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External Communications Lead, IBM Research

Chris Nay

External Communications Lead, IBM Research