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This is the fourth of a four-part series about IBM featured papers at IEDM 2016.
The annual International Electron Devices Meeting is “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” So IBM researchers brought their scanning probe thermometer, their air spacer for a 10 nanometer chip, their 7 nm chip, and not to be out-done by silicon, they brought their carbon nanotubes, too. These papers and presentations by IBMers and many partners will take part in this week’s conference in San Francisco.
IEDM features four IBM papers as some of the conference’s best examples of this re-imagining of computing — extending Moore’s Law, and building new architectures, and using new materials to go beyond it. Here is a closer look at these papers, and the scientists behind the work. The final installment of the series highlights the paper “A 7nm FinFET Technology Featuring EUV Patterning and Dual-Strained High-Mobility Channels”, by Ruilong Xie, a senior member of GlobalFoundries’ technical staff, and members of IBM’s team at the Albany Nanotech Center.
Last July, IBM and its Alliance partners announced they had developed the world’s first 7nm node test chips. The breakthrough came by applying Extreme Ultaviolet (EUV) Lithography – a technique of using light to etch patterns into other materials – and using Silicon Germanium (SiGe) as the channel material in the transistor.
From Silicon to Silicon Germanium
The team’s IEDM paper shows that “SiGe-based FinFET technology demonstrated performance enhancement with 10nm technology ground rules (industry standards), providing elegant solutions towards a viable CMOS technology option. One of those elegant solutions is its allowance for both low power and high performance devices on the same chip – without losing performance or variability on one type of device over the other,” as explained in Material innovation to 7nm.
Further, SiGe pushes the boundaries of chip scaling by changing the way current passes through the channel of a transistor. It turns out that by adding larger germanium atoms to a crystal made of smaller silicon atoms, the crystal develops a lattice mismatch, generating strain in the transistor channel. This strain makes it possible to move more current through the channel at lower voltages. So by using SiGe as a channel material in combination with innovations in parasitic resistance and capacitance reduction, the team could chart a roadmap to a 7nm chip, while maintaining a balance between power and performance — a performance at constant power that, as presented at IEDM, 40 percent better than a 10nm chip!
Extremely small wavelengths of light
The light being used, with only a 13.5 nm wavelength, is much shorter than today’s standard 193 nm wavelength light, making it capable of etching 20 billion 7 nm transistors onto a chip. But before the team can put that many switches on a chip, they need to make the technology behind using such a short wavelength a consistent, controlled, and repeatable process.
To make chips using lithography, a wafer is exposed to a pattern of light much in the same way all non-digital photograph negatives are printed on contact paper – it’s held above the wafer and light is passed through a mask (the ‘negative’). The size of the lines and wires which can be printed using this technique reflect not only the size of the lines on the mask, but also the wavelength of the light being used. Today, using 193 nm light, a wafer may be exposed multiple times if the pattern needed is smaller than what 193 nm can deliver on its own.
So, much like Japanese woodcut printing, pattern after pattern is layered on top of the wafer to get a more intricate – and smaller – chip. This multi-pattern technique, though, causes degradation; which may not be as critical an issue for chips in mass-produced devices such as smartphones, but is a significant roadblock for supercomputers and specialized systems requiring very high reliability. And, while technically possible to make 7 nm chips this way, it’s a big reason why IBM has decided to explore how to make 7 nm chips using EUV technology.
Top left: A schematic description of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the tensile strained silicon fin and (b) the compressively strained SiGe fin on a common SRB. Top right: A TEM image of a 48nm contacted polysilicon pitch device with an optimized self-aligned contact with a contact opening of ~10nm and Lmetal of ~15nm. Bottom middle: illustration and graph show that the trench epitaxial process simultaneously meets ground rules and contact resistivity reduction following implant and anneal optimizations.
Using 13.5 nm EUV, just one high fidelity pattern is needed to print a single pattern on a 7 nm chip. The challenge for EUV is how to mature the technology to be ready for production. Much like how the IBM System 360, built in 1964, led to today’s smaller, faster machines through refinement, scaling and engineering effort, EUV will have to mature in a similar way.
Consider this: to generate 13.5 nm light, the EUV device releases a droplet of molten tin into a vacuum (to get a spherical shape) that is then hit with a Carbon dioxide laser that flattens it and moves it to a specific angle. The tin, still falling, is then hit – and vaporized – with another more-powerful Carbon dioxide laser to release 13.5 nm light, that is then captured and focused onto a wafer using specialized mirrors.
While the process to use this 13.5 nm light is complicated, the teams’ work is proving that making a 7 nm chip using EUV is possible, and provides high quality results. Which should mean that specialized high reliability chips for future high performance systems can be manufactured to meet the demands of next generation supercomputers and systems.
Read part one: Mapping hot spots
Read part two: Another kind of chip with carbon nanotubes
Read part three: Air spacers for 10nm chips