As our semiconductor research team in Albany, NY continues to scale CMOS technology towards future nodes – to 10nm, 7nm, and beyond – the transistor channel resistance that determines current flow, and how we connect to it, continues to play an increasingly significant role in a chip’s overall performance. So in order to ensure the competitiveness of a given future semiconductor technology’s performance, channel material innovation to reduce transistor channel resistance is a critical areas of study. Which is why we are exploring silicon germanium (SiGe) – elements required to achieve the power performance benefits outlined in last year’s 7nm chip announcement.
Today’s 14nm node FinFET*-based chips use silicon-only channels (silicon is not stable beyond this scale). SiGe-based FinFET technology, alternatively, has demonstrated performance enhancement with 10nm technology ground rules (industry standards), providing elegant solutions towards a viable CMOS technology option. One of those elegant SiGe FinFET solutions is its allowance for both low power and high performance devices on the same chip – without losing performance or variability on one type of device over the other.
The SiGe FinFET technology also provides superior electrical reliability versus Si FinFET. And this leads to the improved chip level performance stability than Si FinFET over the chip lifetime. This means that the identical process integration flow is suitable for supercomputer designs as well as mobile designs.
SiGe pushes the boundaries of chip scaling by changing the way current passes through the channel of a transistor. It turns out that by adding larger germanium atoms to a crystal made of smaller silicon atoms, the crystal develops a lattice mismatch, generating strain in the transistor channel. This strain makes it possible to move more current through the channel at lower voltages. So by using SiGe as a channel material, we can chart a roadmap to smaller dimensions while maintaining a balance between power and performance.
SiGe for the nodes ahead: Solving the challenges of producing 10nm & 7nm chips
Strain retention throughout the entire integration flow, along with defect control are two of the major technical challenges for producing SiGe FinFET at 10nm node and below. Transistor channels could lose strain during the thermal annealing processes that activate dopants and stabilizes transistor integrity; or during the source/drain recess processes that form the uniform junction from the top of the Fin to the bottom of the Fin; or even the Fin patterning in specific designs that requires short length Fins.
Defect control is also critical in the mass production of a CMOS technology. With the lattice mismatch between a SiGe channel and its silicon wafer substrate, it is challenging to maintain the required manufacturability defect level across the entire wafer. But with our advanced epitaxial (crystal) growth management, innovative Fin module process integration, and source/drain engineering, we developed solutions to ensure the strain in the channel throughout the entire integration flow, while also maintaining low defectivity in our 10nm and 7nm test nodes.
With this comprehensive SiGe FinFET technology feasibility study at 10nm technology ground rules, we are now working with chip designers and chip makers to mass produce SiGe FinFET technology. I anticipate our SiGe FinFET technology will replace silicon FinFET in the next generation of CMOS technology nodes for computing uses, spanning supercomputers to mobile devices. They could also be used in “more than Moore” applications I cloud and cognitive computing, where low power supply and low power consumption are highly desirable, such as applications in cloud and cognitive computing.
At this year’s IEEE symposium on VLSI (very-large-scale integration) technology, our teams presented a number of novel device, material, and integration innovations centered on using SiGe with 10nm ground rules, and also as a path forward to solve the scaling and performance challenges of the 7nm test node we fabricated last year.
Our presentations covered critical technical features and fundamental process innovation for defectivity control; innovations in gate stack and interfacial layer suitable for SiGe FIN; as well as advanced contact techniques on the SiGe FinFET platform, reported in research paper T2.2 at the VLSI conference. The T4.3 research paper presented the inventive selective germanium oxide scavenging process to build a robust interfacial layer for SiGe channel.
Our research led by Dr. Pouya Hashemi that focuses on the extendibility of SiGe FinFET technology for future higher performance nodes was also presented at VLSI. In the T9.3 research paper, we reported the feasibility of achieving higher performance with higher Ge content and smaller Fin width and further gate stack scaling. VLSI Symposium participants can find these technical papers on the VLSI website. You can also join their Linkedin Group for more information.
T2.2: FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond
T4.3: Selective GeOx-Scavenging from Interfacial Layer on Si1-xGex Channel for High Mobility Si/Si1-xGex CMOS Application
T9.3: Replacement High-K/Metal-Gate High-Ge-Content Strained SiGe FinFETs with High Hole Mobility and Excellent SS and Reliability at Aggressive EOT ~7Å and Scaled Dimensions Down to Sub-4nm Fin Widths
T7.2: Ti and NiPt/Ti Liner Silicide Contacts for Advanced Technologies
*-FinFET refers to a transistor architecture that raises the transistor channel so that it looks like fins)
Dechao Guo is a research staff member, master inventor, and manager of Advanced Device Design & Integration at IBM Research.