Inventors’ Corner: U.S. Patent #7,741,722 – Through-wafer vias

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This patent describes a technique that enables fabrication of vertically stacked, high-performance three-dimensional (3-D) computer chips. The invention creates “through-silicon vias,” which are vertical connections etched through a silicon wafer and filled with metal, to boost the speed at which data flows from chip-to-chip.

The vias enable chips and memory devices that are traditionally placed side-by-side on a wafer to be stacked on top of each other. The vertical stacks eliminate the need for long metal wires that typically connect chips together. This technique significantly reduces the size of a chip package, as well as the distance that information needs to travel on a chip. Consequently, chip components can be packaged much closer together, which results in faster, smaller, and lower-power chips.

IBM is using the patented TSV technique in the production of silicon germanium (SiGe) communications chips, which power amplifiers for cellular handsets, cordless phones, wireless LAN and WiMAX applications. The through-silicon vias can improve power efficiency in SiGe-based wireless products up to 40 percent, which leads to improved performance and longer battery life.

U.S. Patent #7,741,722 was issued to IBM inventors Paul Andry, Edmund Sprogis, Kenneth Stein, Timothy Sullivan, Cornelia Tsang, Ping-Chuan Wang, and Bucknell Webb.

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