Performance considerations with logical partitioning

You can configure POWER4-based systems in a variety of ways, such as larger systems with POWER4 CPUs packaged as Multi Chip Modules (MCM) or smaller systems with POWER4 CPUs packaged as Single Chip Modules (SCM).

Application workloads might vary in their performance characteristics on these systems.

LPAR offers flexible hardware use when the application software does not scale well across large numbers of processors, or when flexibility of the partitions is needed. In these cases, running multiple instances of an application on separate smaller partitions can provide better throughput than running a single large instance of the application. For example, if an application is designed as a single process with little to no threading, it will run fine on a 2-way or 4-way system, but might run into limitations running on larger SMP systems. Rather than redesigning the application to take advantage of the larger number of CPUs, the application can run in a parallel set of smaller CPU partitions.

The performance implications of logical partitioning should be considered when doing detailed, small variation analysis. The hypervisor and firmware handle the mapping of memory, CPUs and adapters for the partition. Applications are generally unaware of where the partition's memory is located, which CPUs have been assigned, or which adapters are in use. There are a number of performance monitoring and tuning considerations for applications with respect to the location of memory to CPUs, sharing L2 and L3 caches, and the overhead of the hypervisor managing the partitioned environment on the system.