CPU Data Section

This section contains general information on CPU use during the interval. Start of changeAll measurements are provided on a per logical processor basis.End of change

Offsets Name Length Format Description
0 0 SMF70WAT 8 binary CPU wait time, where bit 51 = 1 microsecond. That is, the amount of time that the CPU is not processing instructions (PSW wait state bit is on). Data could be incorrect if a SET CLOCK occurred during the RMF™ interval.

SMF70WAT is used in RMF report calculations

Note: This field is incorrect if MVS™ is running under VM.
8 8 SMF70CID 2 binary CPU identification
10 A SMF70CNF 1 binary Configuration activity indicator
Bit
Meaning when set
0-3
Reserved
4
Data available for complete interval
5
CPU reconfigured during post processor duration interval
6
CPU reconfigured during the measurement interval (data for this CPU is incorrect)
7
CPU online at end of interval.
11 B   1   Reserved.
12 C SMF70SER 3 packed CPU serial number (6 hexadecimal digits).
15 F SMF70TYP 1 binary CPU type.
Value
Meaning
0
General purpose CP
1
zAAP
2
zIIP
16 10 SMF70SLH 4 binary Number of entries to the I/O SLIH; number of I/O interruptions that this processor handled by entry into the I/O interrupt handler.
20 14 SMF70TPI 4 binary Number of TPI (test pending interrupt) with CC=1; number of I/O interruptions that this processor handled from issuing the TPI instruction.
24 18 SMF70VFS 4 binary Number of samples when the vector bit in the PSA image was on, which is used to determine the percentage of time vector affinity was on.
28 1C SMF70V 1 binary Vector configuration
Bit
Meaning when set
0
Vector was online
1-7
Reserved.
29 1D   3   Reserved.
32 20 SMF70PAT 8 binary CPU parked time, where bit 51 = 1 microsecond.
40 28 SMF70TCB 8 binary Number of TCB dispatches for this CPU.
48 30 SMF70SRB 8 binary Number of SRB dispatches for this CPU.
56 38 SMF70NIO 8 binary Number of I/Os for this CPU.
64 40 SMF70SIG 8 binary Total number of SIGPs done by this CPU.
72 48 SMF70WTD 8 binary Wait dispatch count for this CPU.
80 50 SMF70WTS 4 binary The number of times PR/SM™ issued a warning-track interruption to a logical processor and z/OS® was able to return the logical processor within the grace period.
84 54 SMF70WTU 4 binary The number of times PR/SM issued a warning-track interruption to a logical processor and z/OS was unable to return the logical processor within the grace period.
88 58 SMF70WTI 4 binary Amount of time in milliseconds that a logical processor was yielded to PR/SM due to warning-track processing.