Consider the number of CPU measurement facility counters for
zEC12 or zBC12. The number of CPU measurement facility counters
for zEC12 and zBC12 is increased to 
128
. More
extended counters means that more internal storage is required. Though
the structure of the SMF 113 record does not change, the values, interpretations,
and frequency of certain sections do change; therefore, current tools
using the data must be updated for the zEC12 or zBC12.
For example, consider the following SMF record field:
- SMF113_2_CtrVN2 identifies how to interpret the Crypto and Extended counter sets. As described in The IBM CPU Measurement Facility Extended Counters Definition for z10™ and z196, SA23-2260, this field is set to 1 (for z10), 2 (for z196 or z114), or 3 (for zEC12 and zBC12).
Note: As of z/OS V2R1, if you use the CPU Measurement
Facility, IBM recommends that your installation collect SMF 113 subtype
1 and 2 records. IBM also recommends that products process SMF 113
subtype 1 records when available, because that is where future enhancements
will be made. If subtype 1 records are not available, products can
process subtype 2 records.
As of z/OS V2R1, if you use the CPU Measurement
Facility, IBM recommends that your installation collect SMF 113 subtype
1 and 2 records. IBM also recommends that products process SMF 113
subtype 1 records when available, because that is where future enhancements
will be made. If subtype 1 records are not available, products can
process subtype 2 records.The following zEC12 and zBC12 functions are available on z/OS V2R1. For PTF information, see the Notes for Table 2:
- CFCC Level 19 Coupling thin interrupt support. With PTFs CFCC Level 19 provides coupling thin interrupt support that allows a shared logical coupling facility partition to be dispatched by PR/SM if not already dispatched and allows for more timely processing of events to which the CF must respond. It is designed to improve service times for shared engine coupling facilities, and to help improve the response time for asynchronous CF operations. This function requires CFCC Level 19.
- Cryptographic Enhancements. Cryptographic enhancements
for z/OS V2R1 on zEC12 and zBC12 server include:
- Crypto Express4S CCA enhancements when the PCIe adapter is configured as CCA coprocessor including: Export TDES key under AES transport key, Diversified Key Generation CBC, IPEK, RKX key wrapping method, and Integration of UDX into CCA requires z/OS V2R1 with the Cryptographic Support for z/OS V1R13-z/OS V2R1 Web deliverable (FMID HCR77A1) installed.
- Crypto Express4S EP11 enhancements when the Crypto Express4S PCIe adapter is configured as an EP11 coprocessor including: (PKCS #11 V2R1 PSS, EP11 Key agreement algorithms, and Offload Generation of Domain Parameters) and requires z/OS V2R1 with the Cryptographic Support for z/OS V1R13-z/OS V2R1 Web deliverable (FMID HCR77A1) to be installed.
- Crypto Express4S (#0865) exploitation including Enterprise Security PKCS #11-Hardware Security Module (HSM), DUKPT for MAC and Data Encryption, Cipher Text Translate CCA Verb, PKDS/TKDS Constraint Relief, Random Number Cache, FIPS on Demand, and Wrapping Keys with Strong Keys.
- zEDC capability using zEDC Express. zEDC provides IBM zEnterprise data compression/decompression capability. For z/OS V2R1, the zEDC software feature must be enabled with your product enablement policy (IFAPRDxx); then follow the z/OS V2R1 documentation to customize the exploiting functions. See Verify your IFAPRDxx Product ID is correct for z/OS Version 2
- IBM® zAware system. IBM zAware is designed to offer a near real-time, continuous learning, and diagnostics capability intended to help you pinpoint and resolve potential problems quickly enough to minimize impacts to your business. After you order a zEC12 or zBC12 you can prepare to set up an IBM zAware environment by defining the IBM zAware logical partition, defining and using OPERLOG log streams, and network definitions to connect the z/OS LPAR to the zAware LPAR. For more information, see IBM System z® Advanced Workload Analysis Reporter (IBM zAware) Guide, (SC27-2623) and z/OS MVS Setting Up a Sysplex.
- Java Exploitation of Transactional Execution (requires Java
7 SR3). This function provides support for Java exploitation of
the Transaction Execution Facility on IBM zEnterprise zEC12 or zBC12.
Transactional Execution will offer increased scalability and parallelism
to drive higher transaction throughput. Java exploitation is planned
with
- IBM 31-bit SDK for z/OS, Java Technology Edition, V7.0.0 (5655-W43)
- IBM 64-bit SDK for z/OS, Java Technology Edition, V7.0.0 (5655-W44).
Note: Using z/OS V1R13 XL C/C++ compiler and later, specify ARCH(10) to provide the hardware with built-in functions to enable applications to use the Java Transactional Execution Facility. - Flash Express (Storage Class Memory or SCM). This support includes pageable 1 MB Large Page support, dynamic reconfiguration support of SCM, and optional PLPA/COMMON page data set usage. This support requires the Flash Express hardware feature.
- 2GB Large Page support. This support includes support for 2 GB large fixed pages.
- CFCC Level 19 Flash Express. This exploitation will provide improved resilience for MQ shared queues. The function requires CFCC Level 19 and is planned to be available in a future update.
- New z/Architecture instructions: XL C/C++ ARCH(10) and TUNE(10) parameters. This function provides new zArchitecture instructions.
- Shared Memory Communications using RDMA (SMC-R) exploitation. Shared Memory Communication using RDMA (Remote Direct Memory Access) enables transparent exploitation of RDMA technology for TCP/IP sockets based applications. It requires the 10GbE RoCE Express hardware feature.
- 24k subchannels per channel (port) for the FICON Express features. This is planned to help facilitate growth as well as continuing to enable server consolidation. You will be able to define more devices per FICON channel, which includes primary, secondary, and alias devices. This support applies to the FICON Express8S, FICON Express8, and FICON Express4 features when defined as CHPID type FC.
- OSA-Express5S. OSA-Express5S provides a new generation of Ethernet features for use in the PCIe I/O drawer and continues to be supported by the 8 GBps PCIe Gen2 host bus. This support includes: 1000BASE-T Ethernet for copper environments, in addition to 10 Gigabit Ethernet (10 GbE) and Gigabit Ethernet (GbE) for single-mode and multimode fiber optic environment.