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Examples of server technologies
patents
 USP 6,859,866 entitled "SYNCHRONIZING PROCESSING OF COMMANDS INVOKED AGAINST DUPLEXED COUPLING FACILITY STRUCTURES"
Distributed computing environments provide for duplexing of structures called coupling facilities which are non-volatile shared storage devices. Failure of these facilities requires significant recovery actions. Thus a proliferation of diverse recovery schemes have been invented. However a need existed for a high-availability coupling facility which improved on recovery times and other impacts of existing recovery techniques. More particularly a need existed for capabilities which facilitated duplexing of structures in separate coupling facilities coupled to one another.
Accordingly, this invention provides a coupling facility which is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on a structure basis, and thus a coupling facility may include duplexed structures as well as non-duplexed or simplexed structures. The invention provides a system and method for synchronizing processing of commands invoked against duplexed coupling facility structures. In one embodiment, a command is provided to be processed against a duplexed coupling facility structure. A signaling engine is further provided to facilitate synchronizing execution of the command against the duplexed coupling facility structure.
USP 6,865,688 entitled "LOGICAL PARTITION MANAGEMENT APPARATUS AND METHOD FOR HANDLING SYSTEM RESET INTERRUPTS"
This invention is directed to a logical partition management apparatus and method for handling system reset interrupts (SRIs). Logical partitioning (LPAR) is a system structure allowing symmetric multiprocessor (SMP) systems to be subdivided into partitions each having necessary processor, memory, and I/O resources to run an operating system image. A firmware hypervisor provides platform management functions for these LPARs. During a hypervisor call, one of these SRI's may occur which, without the invention, would disrupt and end the hypervisor call. Accordingly a mechanism was needed, provided by the invention, in the form of logical partition management apparatus and methods for more effectively handling SRIs occurring at any time during operation of the multiprocessor computing system, including during a hypervisor call, so as to avoid deadlocks and the like.
In accordance with the invention, the system and method allow a hypervisor call to be completed before an SRI is handled. In this way, the SRI does not cause a processor of the SMP system to indefinitely hold a lock on a system resource. Thus other processors are not starved due to inability to access the system resource.
USP 6,907,477 entitled "SYMMETRIC MULTI-PROCESSING SYSTEM UTILIZING A DMAC TO ALLOW ADDRESS TRANSLATION FOR ATTACH PROCESSORS"
This invention relates to the powerful and versatile Cell processor architecture enjoying significant publicity with widely ranging applications from the gaming industry to national defense. Such architecture is a symmetric multi-processor (SMP) system having attached processing units (APU's). APU's in prior art SMP computer architectures did not access shared memory because they were not structurally configured with an address translation mechanism, e.g. a translation lookaside buffer (TLB). The invention provides a system and method for APUs to thus access shared memory in an SMP system. In one embodiment the system includes a shared memory and multiple processing elements coupled to the shared memory. Each of these processing elements comprises a processing unit, direct memory access controller (DMAC), and multiple APU's. Each DMAC comprises a TLB thereby enabling each associated APU to access the shared memory in a restricted manner without an address translation mechanism. Each APU is configured to issue a request to an associated DMAC to access the shared memory, specifying a range of addresses to be accessed as virtual addresses. The associated DMAC is configured to translate the range of virtual addresses into an associated range of physical addresses.
USP 6,973,510 entitled "DMA WINDOWING IN AN LPAR ENVIRONMENT USING DEVICE ARBITRATION LEVEL TO ALLOW MULTIPLE IOAS PER TERMINAL BRIDGE"
Another problem associated with LPAR systems as described above is that I/O subsystems are frequently designed with several I/O adapters (IOAs) sharing a single I/O bus. An operating system image contains device drivers which issue commands controlling their IOA. One such command contains direct memory access (DMA) addresses and lengths for the I/O operation being programmed. Errors in the address or length parameters result in sending or fetching data to or from memory allocated to another operating system image within the system, thereby causing corruption or theft of the data of another operating system image within the data processing system. A need existed for a way to prevent such errors.
Accordingly, the invention achieves this, wherein a system and method are provided for preventing IOAs used by an operating system in an LPAR system from fetching or corrupting data from a memory location allocated to another operating system image. A hypervisor prevents transmission of data between an IOA in one of the logical partitions and memory locations assigned to other logical partitions during a DMA operation by assigning each of the IOAs a range of I/O bus DMA addresses. The IOAs are connected to PCI host bridges via terminal bridges. An arbiter is provided which selects one of the IOAs to use the PCI bus. The terminal bridge may examine the grant signals from the arbiter to the IOAs to determine which set of range registers is to be used.
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