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<title>IBM developerWorks : Multicore acceleration : Tutorials</title>
<link>http://www.ibm.com/developerworks/</link>
<description>The latest content from IBM developerWorks</description>
<pubDate>01 Dec 2009 09:31:23 +0000</pubDate>
<language>en</language>
<copyright>Copyright 2004 IBM Corporation.</copyright>
<image>
<title>developerWorks</title>
<url>http://www.ibm.com/developerworks/i/dwlogo-small.gif</url>
<link>http://www.ibm.com/developerworks/</link>
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	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0 tools, Part 1: Using performance tools]]></title> 
		<description><![CDATA[This introductory tutorial, designed as a companion for the IBM SDK for
      Multicore Acceleration, Version 3.0 (otherwise known as the Cell Broadband
      Engine(R) SDK), teaches you how to use five performance tools that reside in the SDK
      3.0:  OProfile, Cell Performance Counter, Performance Debugging Tool, the PDT Trace
      Reader, and FDPR-Pro. The Visual Performance Analyzer, available separately, is also highlighted.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-sdk3tool.html?ca=drs-]]></link> 
		<pubDate>15 Apr 2008 04:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0, Part 1: Create an SPU project]]></title> 
		<description><![CDATA[This introductory tutorial, designed for the IBM SDK for Multicore
      Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
      explores the Cell/B.E. processor IDE and gives developers a click-for-click
      walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
      project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
      launcher, debugging and doing performance analysis, using simulator consoles,
      using the ALF wizard, and setting IDE preferences.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide30-1.html?ca=drs-]]></link> 
		<pubDate>13 Nov 2007 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0, Part 6: Use simulator consoles, use the ALF wizard, and set IDE preferences]]></title> 
		<description><![CDATA[This introductory tutorial, designed for the IBM SDK for Multicore
      Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
      explores the Cell/B.E. processor IDE and gives developers a click-for-click
      walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
      project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
      launcher, debugging and doing performance analysis, using simulator consoles,
      using the ALF wizard, and setting IDE preferences.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide30-6.html?ca=drs-]]></link> 
		<pubDate>13 Nov 2007 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0, Part 5: Debug and complete dynamic or static performance]]></title> 
		<description><![CDATA[This introductory tutorial, designed for the IBM SDK for Multicore
      Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
      explores the Cell/B.E. processor IDE and gives developers a click-for-click
      walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
      project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
      launcher, debugging and doing performance analysis, using simulator consoles,
      using the ALF wizard, and setting IDE preferences.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide30-5.html?ca=drs-]]></link> 
		<pubDate>13 Nov 2007 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0, Part 4: Configure the application launcher]]></title> 
		<description><![CDATA[This introductory tutorial, designed for the IBM SDK for Multicore
      Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
      explores the Cell/B.E. processor IDE and gives developers a click-for-click
      walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
      project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
      launcher, debugging and doing performance analysis, using simulator consoles,
      using the ALF wizard, and setting IDE preferences.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide30-4.html?ca=drs-]]></link> 
		<pubDate>13 Nov 2007 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0, Part 3: Create the Cell/B.E. simulator environment]]></title> 
		<description><![CDATA[This introductory tutorial, designed for the IBM SDK for Multicore
      Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
      explores the Cell/B.E. processor IDE and gives developers a click-for-click
      walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
      project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
      launcher, debugging and doing performance analysis, using simulator consoles,
      using the ALF wizard, and setting IDE preferences.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide30-3.html?ca=drs-]]></link> 
		<pubDate>13 Nov 2007 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Cell/B.E. SDK 3.0, Part 2: Create a PPU project]]></title> 
		<description><![CDATA[This introductory tutorial, designed for the IBM SDK for Multicore
      Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
      explores the Cell/B.E. processor IDE and gives developers a click-for-click
      walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
      project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
      launcher, debugging and doing performance analysis, using simulator consoles,
      using the ALF wizard, and setting IDE preferences.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide30-2.html?ca=drs-]]></link> 
		<pubDate>13 Nov 2007 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[An introduction to the IDE for the Cell Broadband Engine SDK]]></title> 
		<description><![CDATA[This introductory walk-through, updated for the Cell Broadband Engine (Cell BE) SDK V2.1, explores the Cell BE processor IDE and offers a click-for-click lesson on how to construct a simple project.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cellide.html?ca=drs-]]></link> 
		<pubDate>30 Mar 2007 04:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[An introduction to compiling for the Cell Broadband Engine architecture, Part 1: A bird&apos;s-eye view]]></title> 
		<description><![CDATA[This five-part tutorial series helps you understand the Cell Broadband Engine (Cell BE) architecture and gives you a basic intuition for programming issues on it, insight into the compiler challenges presented by it, and an understanding of the techniques and solutions proposed by the IBM compiler. In Part 1, meet the Cell BE processor from a compiler-writer&apos;s perspective, and get a bird&apos;s-eye view of a number of the unique challenges it poses. Part 1 provides useful background information relevant to the other tutorials in the series.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cbecompile1-i.html?ca=drs-]]></link> 
		<pubDate>07 Feb 2006 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory]]></title> 
		<description><![CDATA[Fifth and last in the &quot;An introduction to compiling for the Cell Broadband Engine architecture&quot; series, this tutorial discusses techniques for managing data in the local store of the Synergistic Processor Elements (SPEs) of a Cell Broadband Engine (Cell BE) processor. Learn particular techniques such as double-buffering and maintaining a reasonably efficient software cache.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cbecompile5-i.html?ca=drs-]]></link> 
		<pubDate>07 Feb 2006 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[An introduction to compiling for the Cell Broadband Engine architecture, Part 4: Partitioning large tasks]]></title> 
		<description><![CDATA[This tutorial, fourth and penultimate in the &quot;An introduction to compiling for the Cell Broadband Engine architecture&quot; series, discusses ways to partition code to run across the multiple cores available in a Cell Broadband Engine (Cell BE) processor. It gives particular attention to efficient partitioning of code to allow larger programs or data sets to be manipulated using the 256KB of local store available on the Synergistic Processor Elements (SPEs).]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cbecompile4-i.html?ca=drs-]]></link> 
		<pubDate>07 Feb 2006 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[An introduction to compiling for the Cell Broadband Engine architecture, Part 3: Make the most of SIMD]]></title> 
		<description><![CDATA[Third in the &quot;An introduction to compiling for the Cell Broadband Engine architecture&quot; series, this tutorial discusses the compiler issues in optimizing code to run efficiently on SIMD-capable processors. In particular, it shows how to optimize code that must run both on the VMX SIMD engine of the PowerPC core of the Cell Broadband Engine (Cell BE) processor, and also on the SIMD-only Synergistic Processor Elements (SPEs).]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cbecompile3-i.html?ca=drs-]]></link> 
		<pubDate>07 Feb 2006 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE]]></title> 
		<description><![CDATA[Second in the &quot;An introduction to compiling for the Cell Broadband Engine architecture&quot; series, this tutorial discusses specific issues in optimizing code to run effectively on the Synergistic Processor Elements (SPEs) in the Cell Broadband Engine (Cell BE) processor.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-cbecompile2-i.html?ca=drs-]]></link> 
		<pubDate>07 Feb 2006 05:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[ChipBench System Level Design]]></title> 
		<description><![CDATA[Use the ChipBench System Level Design tool to create and simulate a design constructed from SystemC models of IBM PowerPC 4xx processor cores.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-chipbench-i.html?ca=drs-]]></link> 
		<pubDate>27 Sep 2005 04:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[SoC design with CoreConnect: 128-bit PLB explained]]></title> 
		<description><![CDATA[CoreConnect is based on three buses: the Device Control Register (DCR), the Processor Local Bus (PLB), and the On-chip Peripheral Bus (OPB). This architecture lets you connect your IP to the bus that&apos;s most suited to it. The objective of this tutorial is to describe the steps required to design a PLB4 IP. PLB4 is the latest 128-bit version of PLB, which is the backbone of CoreConnect. Learn how to design a system-on-chip (SoC) using PLB4, the latest 128-bit version of PLB. Upon completion of this tutorial, you will be able to implement, test, and debug 128-bit PLB IPs for 4xx, 7xx, and 9xx PowerPC cores.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/pa-dw-pa-socdesign-i.html?ca=drs-]]></link> 
		<pubDate>15 Jun 2005 04:00:00 +0000</pubDate>               
	</item>

	<item>
		<title><![CDATA[Build a GCC-based cross compiler for Linux]]></title> 
		<description><![CDATA[Get step-by-step instructions for building a cross-compiler so that you can build and develop applications for an alternative platform. Cross-compilers can be useful in many different situations, such as when you develop applications for embedded platforms.]]></description> 
		<link><![CDATA[http://www.ibm.com/developerworks/edu/l-dw-l-cross-i.html?ca=drs-]]></link> 
		<pubDate>22 Feb 2005 05:00:00 +0000</pubDate>               
	</item>

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