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Cell Broadband Engine resource center
The Cell Broadband Engine (Cell/B.E.) is a new
architecture that extends the 64-bit Power Architecture.
Ideal for compute-intensive tasks like gaming, multimedia, and
physics- or life-sciences and related workloads, the Cell/B.E.
is a single-chip multiprocessor no bigger than a
fingernail.
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27 Oct 2008 |
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New to Cell/B.E., multicore, and Power Architecture technology
The Multicore acceleration technology zone on developerWorks contains
articles, tutorials, and tips to help developers with Cell Broadband
Engine(TM), multicore, and Power Architecture(TM) application development,
optimization, and migration. For users trying to find their way in a new
topic, all of that information can be overwhelming. This page provides an
overview for readers who would like to learn about this technology but don't
know where to start.
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12 Feb 2008 |
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IBM microNews
06 April 2007
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06 Apr 2007 |
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IBM microNews
23 March 2007
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09 Mar 2007 |
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IBM microNews
09 March 2007
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09 Mar 2007 |
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IBM microNews
06 April 2007
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06 Apr 2007 |
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IBM microNews
23 February 2007
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23 Feb 2007 |
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Page has permanently moved...
This information has been updated for Version 2.0 of the Cell Broadband Engine SDK and is now superseded by two documents, which you can access from the links below. We apologize for any inconvenience.
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12 Jul 2006 |
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Page has permanently moved...
This information has been updated for Version 2.0 of the Cell Broadband Engine SDK and is now superseded by two documents, which you can access from the links below. We apologize for any inconvenience.
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12 Jul 2006 |
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Page has permanently moved...
This information has been updated for Version 2.0 of the Cell Broadband Engine SDK and is now superseded by two documents, which you can access from the links below. We apologize for any inconvenience.
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12 Jul 2006 |
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Forums and community
Get involved in the developerWorks Power Architecture technology community by participating in discussion forums and newsgroups.
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30 Sep 2004 |
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Training
Start here to find the tutorials and courses you need to stay up-to-date with Power Architecture technology and to keep your skills top notch.
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30 Sep 2004 |
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Redbooks
IBM Redbooks are developed and published by the IBM International Technical Support Organization, the ITSO. ITSO develops and delivers skills, technical know-how, and materials to technical professionals of IBM, Business Partners, and customers.
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30 Sep 2004 |
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Redbooks
IBM Redbooks are developed and published by the IBM International Technical Support Organization, the ITSO. ITSO develops and delivers skills, technical know-how, and materials to technical professionals of IBM, Business Partners, and customers.
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30 Sep 2004 |
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Standards and specs: An unsung hero: The hardworking ELF
The ELF object module format has had wide-ranging effects on software development for multiple platforms. Peter Seebach looks at the history of the ELF specification and why it's been so useful.
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20 Dec 2005 |
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Testing and measuring the TAMS 3011, Part 3: Porting a screen-management utility to eCos
See the process of porting the Berkeley curses library from UNIX to eCos, picking up a few fragments of the Berkeley C library extensions along the way -- and learn about some general issues of porting from UNIX to eCos.
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24 Mar 2006 |
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Power Architecture downloads and documentation: Upgrade your Cell BE SDK components
Download new and improved Cell Broadband Engine (Cell BE) SDK components -- the Full-System Simulator, the Software Sample and Library Source Code, and the XL C Alpha Edition compiler. Try out the latest Watson Sparse Matrix Package with a new symmetric indefinite solver with diagonal pivoting. Plus, read more on z9 109, z/OS, p5, and the IntelliStation POWER 185, and get the 750GX/GL Evaluation Board Schematics. And plan your summer Redbooks residency.
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24 Mar 2006 |
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Migrating from x86 to PowerPC, Part 9: Sensors, sensors, sensors!
From schematics to code, get a leg up on building your own robot submarine.
Building on previous successes, Lewin Edwards shows how to add more sensors to your
submarine, looking at the design requirements of different sensors and ways of
sanity checking the results they provide.
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14 Mar 2006 |
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Testing and measuring the TAMS 3011, Part 2: An introduction to eCos
The eCos embedded operating system offers an alternative to UNIX-style operating systems for development work. This article examines how its architecture influences the development process, building a sample application and exploring the differences in architecture between eCos and UNIX.
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24 Feb 2006 |
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SoC drawer: Shared resource management
The goal of a system-on-a-chip (SoC) is to provide a single-chip system, and therefore SoC resource analysis and sizing is critical. Failure to properly size processing, memory, or I/O needed by software services can kill an SoC project. But all too often, SoC design analysis focuses on processing at the expense of memory or I/O sizing. And even when memory and I/O are sized properly, efficient use of these resources by software services can still be tricky. Any mis-sizing or mismanagement of memory and I/O on an SoC can at the least cause significant project delay and rework. This article examines sizing estimation and resource sharing pitfalls that the system architect should know well.
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21 Feb 2006 |
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Meet the experts: An interview with the compiler
Got questions about optimizing code for the Cell Broadband Engine (Cell BE) processor? Questions like, when to inline? When to insert an ifetch--and when to inline an ifetch (and what IS an ifetch?) And where do no-ops go? These questions and many others will be addressed in this exclusive Q and A session.
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14 Feb 2006 |
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Everything you ever wanted to know about C types, Part 2: Floating point and derived types
The C type system is often misunderstood or overlooked. This article, the second in a series, discusses the derived types, or types that are built from other types, and some of the interactions that occur when data of multiple types are mixed.
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14 Feb 2006 |
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Power Architecture directions: Power.org at the one-year crossroads
As Power.org celebrates its first birthday, take a look at what happened in year one and what's ahead. MacLaren Harris interviews Marketing Programs Manager for Power.org Jesse Stein and discovers what is working and what needs work; how Power.org has grown and what has been achieved; and how individual developers can participate.
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27 Jan 2006 |
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PowerPC Architecture Book, Version 2.02
This three-volume set, Version 2.02, defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions for the IBM POWER5 processor family. Verson 2.01 describes POWER4 and POWER4+ processors.
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16 Nov 2005 |
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PowerPC Architecture Book
This three-volume set defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions.
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16 Nov 2005 |
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Power Architecture technology drives development platform
Power Architecture technology offers powerful performance at a low cost, making it the perfect candidate for an embedded development platform. In this article, Viren Shah of Marvell discusses accelerating product development using Discovery LT.
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15 Sep 2005 |
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Power Architecture directions: Future directions and how to get there -- with Power Architecture technology
In this interview, Dr. Bijan Davari talks to McLaren Harris about his vision on how the role of the processor is changing in today's systems.
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16 Sep 2005 |
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SoC drawer: Real-time resource management
Systems-on-chips (SoCs) can support applications ranging from those that simply need to maximize throughput to those that must meet hard real-time deadlines. This article gives an in-depth look at SoC design for real-time applications. Get a review of best-effort, soft real-time, and hard real-time requirements, along with a detailed examination of how an SoC can best support traditional real-time scheduling policies and resource feasibility testing.
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17 Jan 2006 |
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Multifunction multimedia machine, Part 3: Scripting and scaling for fun and profit
Lewin Edwards looks at the history and design of X and why it matters for an embedded graphics system and introduces a basic scripting language for controlling a multimedia display device.
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10 Jan 2006 |
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Everything you ever wanted to know about C types, Part 1: What's in a type?
This article, first in a four-part series, introduces the basics of the C type system, with an overview of what it means to talk about type and a discussion of the basic types (integer and floating point) in some detail.
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03 Jan 2006 |
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SoC drawer: SoC concurrent development
A system-on-a-chip (SoC) can be more complex in terms of hardware-software interfacing than many earlier embedded systems because an SoC often includes multiple processor cores and numerous I/ O interfaces. The process of integrating and testing the firmware-hardware interface can begin early, but without good management and testing, the mutability of firmware and early stages of hardware design simulation can lead to disastrous setbacks for a project. This article teaches system designers about tools and methods to minimize project churn.
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20 Dec 2005 |
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Optimizing the development process
The Power Architecture technology-based Wind River General Purpose Platform, VxWorks Edition, is an excellent base for developers looking to build embedded applications. Leo Samson talks about the latest generation of the product.
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15 Sep 2005 |
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The year in Power Architecture technology: The year in microprocessors
From spintronics to clockless CPUs, 2004 was a year of process and research in the microprocessor industry. This article offers a month-by-month look at the highlights of the 2004 microprocessor timeline.
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22 Dec 2004 |
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Standards and specs: The nitty-gritty on the C committee
The C standard is a few hundred pages full of specifications and requirements. This month's Standards and specs looks at some of the different components of the C standard, and how they might affect Power Architecture developers and implementors.
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23 Nov 2004 |
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Standards and specs: Open Firmware -- the bridge between power-up and OS
Open Firmware provides a reasonably standardized way for computers to find hardware, configure it, and boot an operating system. In this month's Standards and specs, author Peter Seebach looks at the Open Firmware spec, traces its history as a standard, examines how it works and some of its components, and discusses the benefits it offers.
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26 Oct 2004 |
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Standards and specs: Standards
Introducing a regular column on the specifications and standards affecting people involved in nearly every aspect of Power Architecture technology, Peter Seebach looks at the different kinds of standards in the industry today, as well as how to find out about and make the most effective use of standards in your own work.
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27 Sep 2004 |
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From the stacks: Making the transition to 64 bits
Developers porting applications to the 64-bit computing mode of the 970FX processor may face a number of issues; this excerpt from a longer Technical Library article covers some of the issues faced when porting existing 32-bit code to the new computing model -- or when embarking on new 64-bit development.
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19 Oct 2004 |
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Meet the experts: John McCalpin
This question and answer article features IBM Senior Technical Staff Member John McCalpin on his work on the POWER5 and in high performance computing; on the Hypervisor and the size of POWER5 chips; on 128-bit computing -- and even on why he became a computer scientist instead of an entomologist.
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23 Nov 2004 |
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Fun with ALF, Part 6: Using task dependency
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task dependency in a two-stage pipeline
application. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
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22 Jul 2008 |
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Emulation and cross-development for PowerPC
This article introduces PowerPC emulation and cross-compiling for developers without access to real hardware. It is intended for developers familiar with computer architecture who own an x86-based workstation but are interested in experimenting with PowerPC.
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18 Jan 2005 |
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From the stacks: PowerPC 750FX/GX design and debug tips, Part 2
In the second and final installment of this series, IBM Senior Engineer Dale Elson offers comprehensive tips on troubleshooting and debugging your PowerPC 750FX/GX systems. Part 1 focused on design best practices. This article also covers system qualification and lists the information to communicate when you need debugging help.
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12 Oct 2004 |
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From the stacks: PowerPC 750FX/GX design and debug tips, Part 1
Soak up some of the wisdom that the IBM PowerPC Applications Engineering team has accumulated from dozens of years of designing, troubleshooting, and debugging PowerPC systems. In the first of a two-part series, IBM Senior Engineer Dale Elson presents tips and best practices for designing applications for PowerPC 750FX/GX processors -- but you can extrapolate much of his advice to other systems as well.
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06 Oct 2004 |
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Power Architecture author FAQ
If you're interested enough in Power Architecture technology to read articles on our content area, then you just might have some knowledge to share with your fellow pros. Find out how you can submit your ideas to developerWorks.
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18 Feb 2005 |
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From the stacks: TCP/IP checksum vectorization using AltiVec, Part 2
This article, the second in a two-part series, focuses on unrolling loops in ways that allow the AltiVec unit to execute code more efficiently and give the GCC compiler hints for automatically generating vectorized code from plain C.
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02 Nov 2004 |
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Save your code from meltdown using PowerPC atomic instructions
Something as simple as incrementing an integer can fail in a concurrent environment. This article illustrates the failure scenario and introduces the PowerPC's coping mechanism: atomic instructions. Learn how to use these assembly-level instructions to update memory correctly, even in the face of concurrency.
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02 Nov 2004 |
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Standards and specs, Special Edition: Introducing Power.org
Major electronics companies have come together to form a new standards body focused on Power Architecture technology. This organization will create and promote a family of standards, reference designs, and more. This month's Standards and specs looks at how the new standards body will work, and what it will do.
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15 Dec 2004 |
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PowerPC development from the bargain basement
The Kuro Box promises something fairly interesting: a usable single-board PowerPC computer, for only US$160 -- when other PowerPC development boards often cost ten times as much. Peter Seebach guides you through setup and install in this developerWorks hardware howto.
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14 Dec 2004 |
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About: Power.org
This interview focuses on the structure and aims of Power.org, a major new standards consortium in the marketplace. Discover what this new body has to do with open standards, customizable processors, consumer devices -- and doughnuts.
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02 Dec 2004 |
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From the stacks: TCP/IP checksum vectorization using AltiVec, Part 1
This two-part article demonstrates the kinds of performance gains AltiVec can produce on the TCP/IP checksum, or on code similar to it. It gives special attention both to instructions that help improve performance, and to general unrolling and scheduling techniques. The net result? Performance increased by a factor of four.
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26 Oct 2004 |
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Understanding 64-bit PowerPC architecture
Each of the leading microprocessor manufacturers has announced the availability of one or more 64-bit desktop processors, but differences exist in architectural design, fabrication, support, and intended use of each processor. This article looks at the critical issues in a few of IBM's 64-bit POWER designs, covering 32-bit compatibility, power management, processor bus design, and the manufacturing process.
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19 Oct 2004 |
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The IBM PowerPC 970FX power envelope and power management
For potent chips like the PowerPC 970 FX, power consumption is a real concern.This article looks at the power envelope for IBM's PowerPC 970FX processor to give you an understanding of the processor's power management techniques. See how the chip's power-tuning capabilities, along with the several power-saving modes available, allow for an overall reduction in power consumption.
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15 Oct 2004 |
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Frequency switching improves power management in Power Architecture chips
IBM first introduced power-saving, frequency-shifting techniques in its PowerPC 750 line of processors. As process geometries have shrunk further, power dissipation has become even more of a challenge, and IBM engineers have worked hard to improve power-saving technologies and maintain performance. Read on to find out how these techniques have advanced in latest chips from IBM.
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15 Oct 2004 |
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Cell/B.E. SDK: Code sample directory
In this article, you'll find tables indicating the locations of code
samples that illustrate how to use the IBM SDK for Multicore Acceleration.
This article will be updated with new code samples.
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15 Jul 2008 |
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BladeCenter QS: Maximizing memory performance
This article compares the CBEA processor memory access
model (with a focus on the IBM BladeCenter(R) QS21 and QS22) with that of general
purpose processors, providing programmer guidelines to ensure that
applications can be developed for maximum memory performance. This article also
describes how to use the Cell Performance Counter tool when
monitoring memory access activities for tuning and debugging memory
performance.
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01 Jul 2008 |
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Core partners, Part 4: Managing the PlayStation 3 Wi-Fi network
Terra Soft Solutions IT Manager Aaron Johnson shows you, step-by-step, how to configure and encrypt the built-in Wi-Fi network that comes with the
Cell Broadband Engine(TM)-based Sony PlayStation 3. And, as a little bonus, get 16 quick
steps that explain how to switch from a wireless network back to a wired network on the PS3.
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17 Jun 2008 |
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The little broadband engine that could: Rendering fractals on the SPE
In the previous article in the series, you learned some reasons why there
were no appreciable performance gains when you migrated the
fractal-rendering program from running on one SPE to running on multiple SPEs. This
article is going to illuminate the
challenge of rendering fractals on the SPE. The focus is on the SPEs copying their
rendering results directly into the target data buffer.
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10 Jun 2008 |
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The little broadband engine that could: Looking at some DaCS performance fine-tuning issues
In the previous article in the series, you migrated a fractal-rendering program from earlier in the
series to run using the DaCS data library with no appreciable performance gains when
going from running on one SPE to running on multiple SPEs. This article explores ways to optimize
performance.
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20 May 2008 |
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Evaluating IBM BladeCenter QS21 hardware performance
Although there is extensive published data about the hardware performance
features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a
multitude of applications ported to it), there is little on the specific hardware
performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two
Cell/B.E processors as well as an elaborate IO subsystem. In this article, the
authors close that gap by providing information about basic latencies, throughputs,
and relative execution times for some key computational benchmark kernels, such as
Linpack and SPEC2000. The article also delivers a basic architectural overview of
the system. And, you can get tips on how to optimize application
performance.
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06 May 2008 |
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IBM BladeCenter QS21 hardware performance glossary
Although there is extensive published data about the hardware performance
features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a
multitude of applications ported to it), there is little on the specific hardware
performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two
Cell/B.E processors as well as an elaborate IO subsystem. This glossary goes with
the article "Evaluating IBM BladeCenter QS21 hardware performance."
In that article, the
authors close the performance gap by providing information about basic latencies, throughputs,
and relative execution times for some key computational benchmark kernels, such as
Linpack and SPEC2000. The article also delivers a basic architectural overview of
the system. And, you can get tips on how to optimize application
performance.
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06 May 2008 |
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Fun with ALF, Part 4: Determining the dot product of large vectors
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) bundled work block distribution and
the task context to manage situations in which the work block cannot hold the
partitioned data because of a local memory size limit. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
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09 May 2008 |
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Fun with ALF, Part 3: Finding minimum and maximum values
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task context to keep the partial computing
results for each task instance and then combine them. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
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29 Apr 2008 |
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The little broadband engine that could: DaCS--flexible and complex
In an earlier article in this series, the author introduced a fractal-generation
program built around the IDL interface that showcased the strength of IDL's
straightforward API. Executing the program was almost like calling a function and
getting results. In this article (and using the same basic program), the author
demonstrates the Data Communication and Synchronization library's (DaCS) greater
flexibility and the tradeoff: additional complexity. With DaCS, it's possible to pass the fractal pattern in as an initial argument,
then use buffers to pass data back and forth as they are processed. While this requires
more design work, but it might actually be more efficient. This article also shows that DaCS allows
for much more carefully tuned inputs and outputs.
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22 Apr 2008 |
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Linux development on the PlayStation 3, Part 3: Slimming down X11 with tiny tools
The Sony PlayStation 3 (PS3) runs Linux, but getting it to run well requires
some tweaking. In the third and final article of this series on PS3 Linux, Peter
Seebach talks about ways to get X11 slimmed down to fit on a smaller memory budget.
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08 Apr 2008 |
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Core partners, Part 3: Transforming Gedae-built portable apps
This concise study examines the portability of
applications developed in Gedae by analyzing the work required to move an example
application from a simulation on a PC to actually running on a DSP board (the
Mercury Computer System AdapDev system) to running on a multicore Cell Broadband
Engine(TM) (Cell/B.E.). The article illustrates how architecture considerations were taken into account
when porting the application to each system. You can see the amount of work required to
port the application and the performance of the application on each system.
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08 Apr 2008 |
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Linux development on the PlayStation 3, Part 2: Working with memory
The Sony PlayStation 3 (PS3) runs Linux, but getting it to run well requires
some tweaking. In this article, the second in a series, Peter Seebach takes a look
at where all the memory goes and how to reclaim it.
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31 Mar 2008 |
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Fun with ALF, Part 2: Converting I/O data
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task context buffer as a large lookup table to
convert the 16-bit input data to 8-bit output data. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
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25 Mar 2008 |
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Linux development on the PlayStation 3, Part 1: More than a toy
The Sony PlayStation 3 (PS3) runs Linux, but getting it to run well requires
some tweaking. In this article, first in a series, Peter Seebach introduces the
features and benefits of PS3 Linux, and explains some of the issues that might
benefit from a bit of tweaking.
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18 Mar 2008 |
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Fun with ALF, Part 1: Adding large matrices together
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) in the IBM SDK for Multicore Acceleration 3.0 to
add two large matrices together. There is one example for host data
partitioning and one for accelerator data partitioning. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
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18 Mar 2008 |
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The little broadband engine that could: IDL is dead--long live DaCS!
In SDK 3.0, the Data Communication and Synchronization library (DaCS)
provides a sparkling substitute for IDL. DaCS is a set of services to aid the development
of applications and application frameworks in a heterogeneous multi-tiered system.
This article takes you on a tour of the DaCS process model and
explores general DaCS principles, including communication and memory access.
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04 Mar 2008 |
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The little broadband engine that could: Reviewing the newest little SDK that installs natively on PS3
Come along on a little train tour of the SDK for Multicore Acceleration 3.0
to see what's different for developers and how you can make good use of the SDK,
including native installation on PS3, support for FC7 and RHEL 5.1, enhanced compilers,
Fortran and Ada support, BLAS, ALF, and DaCS--oh my!
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19 Feb 2008 |
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Core partners, Part 2: Using DDT to clean up Cell/B.E. app bugs
Allinea Software's Distributed Debugging Tool (DDT)
provides an easy-to-use, capable debugger that is able to debug complete Cell
Broadband Engine applications, including multiple threads within a single Cell/B.E.
processor and clusters of Cell/B.E. processors.
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05 Feb 2008 |
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Cell/B.E. container virtualization, Part 2: Implementation issues
This three-part series illustrates a
hardware-resource-focused form of software virtualization known as container
virtualization (or operating system virtualization), demonstrated through the open
source project OpenVZ. The series provides a comprehensive overview of all the
components and techniques needed to virtualize the Cell/B.E. processor with software
methods. This second article of the series details the implementation of
dedicated virtualization and partitioning that was described in Part 1 of the series.
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08 Jan 2008 |
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Cell/B.E. container virtualization, Part 1: Concepts, architectures, and tools
This three-part series illustrates a
hardware-resource-focused form of software virtualization known as container
virtualization (or operating system virtualization), demonstrated through the open
source project OpenVZ. The series provides a comprehensive overview of all the
components and techniques needed to virtualize the Cell/B.E. processor with software
methods. This first article of the series discusses the basic concepts
involved, illustrates the salient points of the OpenVZ and Cell/B.E. architectures
and how they work together, and describes some of the OpenVZ tools.
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11 Dec 2007 |
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Porting workshop, Part 7: Getting the most performance
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In part seven, the authors evaluate the performance data to date.
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06 Nov 2007 |
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Minimize recoding impact, Part 2: Removing obstacles to speedy performance
The first article in the series describes how to do a basic port to the Cell Broadband Engine process. This
second article goes further in hammering out the details, including removing limitations
based on DMA-transfer size, partitioning the program across multiple SPEs, and
improving the program's speed even more.
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16 Oct 2007 |
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IBM Installation Toolkit: Loading Linux on POWER
The IBM Installation Toolkit for Linux on POWER simplifies the installation of Linux on
virtualized and non-virtualized Power machines, gives you a bootable rescue DVD, and
provides the software needed to fully exploit the Power platform. Learn to use the
toolkit to install Red Hat Enterprise Linux and SUSE Linux Enterprise Server on
IBM System p and System
i5 machines.
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26 Sep 2007 |
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Porting workshop, Part 6: Tying it all together
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In this Part 6, the authors provide a summary of what the series has
covered so far.
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16 Oct 2007 |
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Porting workshop, Part 5: Mixed-precision workloads
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In this Part 5, the authors determine how to make mixed-precision
calculations work with the sample application.
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02 Oct 2007 |
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PS3 fab-to-lab, Part 2: Generating and analyzing signals
How do you take the Cell Broadband Engine (Cell/B.E.) processor from an
off-the-shelf Sony PLAYSTATION 3 (PS3) and use it to construct a piece of
Linux(R)-based laboratory equipment (in essence, take the Cell/B.E. from fab to hab
to lab)? In this series, Lewin Edwards shows you how to go from game console to
simple audio-bandwidth spectrum analyzer and function generator. In this article,
the author shows you how to build on the infrastructure from Part 1 to make the
system into a fully operational, if primitive, spectrum analyzer.
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02 Oct 2007 |
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Porting workshop, Part 4: Mersenne-Twister
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In this Part 4, the authors explore the Mersenne-Twister random-number
generator to determine its effect.
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18 Sep 2007 |
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The little broadband engine that could: Use multiple SPEs for a single task
Peter Seebach uses a simple, iterative-function fractal generator program to describe how to use multiple
Synergistic Processor Engines (SPEs) to vectorize a single task using the job queue model.
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18 Sep 2007 |
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Minimize recoding impact, Part 1: How to make an SPE and existing code work together
Traditional porting requires identifying and abstracting out the
architecture-dependent code: making code endian-independent, working through minor
API differences, and including the appropriate header files and libraries. While
this procedure works for getting code to run on the Cell Broadband Engine
(Cell/B.E.) processor, to actually use the extra processing elements, you have to
put in extra work, including reworking the code and rethinking the build process. In
this series, learn to take advantage of the Synergistic
Processor Elements (SPEs) in existing code and only make a minimal impact to the existing code and build process.
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04 Sep 2007 |
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Porting workshop, Part 3: Initial performance results
The seven, quick-read parts of this series, "Porting workshop," take you on a real-world trip from strategy and planning through workload execution through performance tweaking through optimization to a solid conclusion -- how to most effectively port compute-intensive applications to the Cell Broadband Engine platform. In part three, the authors run and review performance tests and data on the modified code.
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04 Sep 2007 |
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Porting workshop, Part 2: Original code analysis
The seven, quick-read parts of this series, "Porting workshop," take you on a real-world trip from strategy and planning through workload execution through performance tweaking through optimization to a solid conclusion -- how to most effectively port compute-intensive applications to the Cell Broadband Engine platform. In part two, explore the original code with Linux profiling tools.
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07 Aug 2007 |
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The little broadband engine that could: Why is my scalar code so slow?
The SIMD-only architecture of the Cell Broadband Engine (Cell/B.E.)
processor's Synergistic Processor Engine (SPE) is an architecture that has no scalar
operations -- all operations are performed on 16-byte vectors. Design code that helps
the Cell/B.E. compiler make efficient use of this architecture.
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07 Aug 2007 |
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Porting workshop, Part 1: Processor porting strategies
The seven, quick-read parts of this series, "Porting workshop," take you on
a real-world trip from strategy and planning through workload execution through
performance tweaking through optimization to a solid conclusion -- how to most
effectively port compute-intensive applications to the Cell Broadband Engine
platform. In part one, discover the top three strategies for porting.
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07 Aug 2007 |
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Fun with ALF, Part 5: Using overlapped I/O buffers to add matrices
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) overlapped input-output buffers to perform
matrix addition. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
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03 Jun 2008 |
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Changes in libspe: How libspe2 affects Cell Broadband Engine programming
The standard library that Power Processor Element (PPE) programs use to
access and manage Synergistic Processor Elements (SPEs), called
libspe, has undergone a major revision. The Cell Broadband Engine (Cell/B.E.)
SDK 2.1 officially changes the library interface from libspe1 to libspe2. In
this article, Jonathan Bartlett introduces the libspe2 concepts and shows how to do basic SPE process management and communication with libspe2.
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17 Jul 2007 |
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The little broadband engine that could: Mailboxes and interrupts
Meet two more means of communication between the SPE and the PPE -- mailboxes
and signal notification. Mailboxes are special-purpose registers, similar to the I/O
registers used to communicate with peripheral devices on some systems, available on the SPEs and the PPE. Signal notification registers are registers which can be read or written to by the PPE, but which the SPE can only read.
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03 Jul 2007 |
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Porting practices: Compute-intensive applications
The Cell Broadband
Engine (Cell/B.E.) processor has powerful computation capabilities, but to fully
unleash its power, you need to provide a unique programming paradigm. In this article,
learn best practices for porting a JPEG compression application to the Cell/B.E.
Synergistic Processor Engine (SPE), and see how to take advantage of the processor's unique architecture and avoid its shortcomings.
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19 Jun 2007 |
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Tech tips: Ten helpful tips when building SPE applications in C
These ten tips can save you
a lot of trouble when you're coding your C applications for the Cell Broadband
Engine (Cell/B.E.) SPU.
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05 Jun 2007 |
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The little broadband engine that could: An introduction to using SPEs for Cell Broadband Engine development
In this first article in a series on Cell Broadband Engine (Cell/B.E.) development, Peter
Seebach introduces the API used to run programs on SPEs, focusing specifically on
loading code on an SPE and sending data to it for processing.
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05 Jun 2007 |
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PS3 fab-to-lab, Part 1: Build Linux lab equipment from a Sony PLAYSTATION 3
How do you take the Cell Broadband Engine (Cell/B.E.) processor from an
off-the-shelf Sony PLAYSTATION 3 (PS3) and use it to construct a piece of
Linux-based laboratory equipment (in essence, taking the Cell/B.E. from fab to hab
to lab)? In this series, Lewin Edwards shows you how to go from game console to
simple audio-bandwidth spectrum analyzer and function generator. First up, uncover
the design intent of the project and then make a close inspection of the details of
the user interface implementation as you start a journey to generate and analyze
signals on the Cell/B.E. processor.
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15 May 2007 |
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Tech tips: SPU vector intrinsics at your fingertips
Know these common C/C++ language extensions intrinsics and greatly simplify the arduous task of using the SPU's assembly language.
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01 May 2007 |
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Core partners, Part 1: Build high-performance apps for multicore processors
The RapidMind Development Platform provides a simple single-source mechanism to develop portable high-performance applications for multicore processors. In particular, you can use it to develop applications that fully exploit the power of the Cell Broadband Engine (Cell/B.E.) processor's unique architecture by writing only one, single-threaded C++ program using an existing C++ compiler. In this article, author Michael McCool takes you on a guided tour of the RapidMind Development Platform.
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01 May 2007 |
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Massively multiplayer online games, Part 1: A performance-based approach to sizing infrastructure
Massively multiplayer online games (MMOGs) are some of the most complicated software systems under development today, often requiring dozens of developers, hundreds of artists, and truly massive infrastructures. This article is the first in a series of articles that will shine a light on the systems, storage, and networks needed to run an MMOG. It provides an introduction to MMOGs and demonstrates one approach to sizing a game's infrastructure. Learn how to figure out how much infrastructure you might need, as well as how to operate an MMOG.
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10 Apr 2007 |
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Clustering solutions for Linux on IBM System p5 Express servers
Learn how to build a Linux High Availability (HA) cluster and a High Performance Computing (HPC) cluster on IBM POWER processor-based servers.
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02 Nov 2005 |
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The Power Architecture Time Base register in 64-bit Linux
Use the Power Architecture technology's Time Base register to measure time at the nanosecond level in Linux on PowerPC and Cell Broadband Engine (Cell/B.E.) microprocessors. Applications where this is useful include timestamping transactions (typically encrypted or digitally signed single-use messages), profiling code, and implementing small, precise software delays.
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04 Apr 2007 |
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Programming high-performance applications on the Cell/B.E. processor, Part 6: Smart buffer management with DMA transfers
Explore the concepts of double-buffering and multibuffering to improve code speed by parallelizing processing and data transfer, and allowing the SPE's memory flow controller (MFC) to coordinate the best order of operations for loading and storing.
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03 Apr 2007 |
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The Heath Robinson Rube Goldberg Computer, Part 4: The battle to make the virtual cabinets work
Nothing is as easy as one might hope. Since the last article was posted, the Heath Robinson Rube Goldberg (HRRG) Computer team has been battling every step of the way to bring the HRRG emulator's virtual cabinets online. On the way, we've re-engineered everything several times, and run across some unanticipated scenarios...
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20 Mar 2007 |
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