 |
|
|
|
|
|
IBM PowerPC 405 Evaluation Kit with CoreConnect SystemC TLMs
The PowerPC Evaluation Kit is no longer available from
developerWorks.
|
|
Articles |
|
29 Jul 2009 |
|
| |
Automating deployment and activation of virtual appliances for IBM AIX and Power Systems
Server virtualization enables you to rapidly provision new environments by
using libraries of virtual image templates, or virtual appliances. Automated
provisioning requires the management of operating system, network, and
application-specific customization. This article provides a sample framework for
automating virtual image deployment and activation on Power Systems, with a
downloadable example that demonstrates how to provision a virtual appliance made up
of IBM WebSphere Application Server V7.0 running on AIX V5.3.
|
|
Articles |
|
29 Apr 2009 |
|
| |
developerWorks Multicore acceleration zone changes
The Multicore acceleration zone on developerWorks is no longer
publishing weekly content.
|
|
Articles |
|
13 Mar 2009 |
|
| |
A close-up of SDK 3.1, Part 2: Building examples with make.footer
The Cell/B.E. SDK 3.1 supports a pseudo "build environment" by including
a make.footer file that you can include in a makefile to help you build
examples and demonstrations. In this article, you can read about some of the
features and functions available in the make.footer file and how they are used
to construct the SDK examples.
|
|
Articles |
|
25 Nov 2008 |
|
| |
Debugging common DMA errors
To access main storage, Cell Broadband Engine(TM) SPEs use direct memory
access commands (DMA), which transfer data between the main storage and their
private local memory. Although this organization of distributed storage
promotes high performance, it requires the SPE programmer to explicitly handle
the DMA transfers between main and local storage. Errors during these
transfers can be difficult to detect and debug. This article
provides techniques for handling common problems with SPE-initiated DMA
transfers.
|
|
Articles |
|
04 Nov 2008 |
|
| |
Cell Broadband Engine resource center
The Cell Broadband Engine (Cell/B.E.) is a new
architecture that extends the 64-bit Power Architecture.
Ideal for compute-intensive tasks like gaming, multimedia, and
physics- or life-sciences and related workloads, the Cell/B.E.
is a single-chip multiprocessor no bigger than a
fingernail.
|
|
|
|
27 Oct 2008 |
|
| |
Programmability, Part 1: Exploring different approaches to programming for Cell/B.E. platforms
The programming flexibility available for the Cell Broadband Engine(TM) is a
hot topic in the multicore community. This article discusses leveraging your existing
skills to program for Cell/B.E.(TM), offers three programming approaches for Cell/B.E.
systems, and introduces the various tools, software, and hardware available
for the platform.
|
|
Articles |
|
14 Oct 2008 |
|
| |
TechReview, Part 2: Program applications with the LAPACK library
For application programmers using the IBM Software Development
Kit for Multicore Acceleration (SDK), this article explains how to program
with the IBM Linear Algebra Package (LAPACK) library using a sample application
designed to get an inverse matrix. The article also offers 4 pieces of advice on optimizing
LAPACK programs, and it outlines the package's optimized APIs. LAPACK is based
on a published standard interface for commonly used linear algebra
operations in high-performance computing and other scientific domains.
|
|
Articles |
|
30 Sep 2008 |
|
| |
Enabling applications, Part 1: Is your application ready for Cell/B.E.?
Learn from the experts how to evaluate your application's
appropriateness for the Cell/B.E.(TM) platform from the standpoints of
performance and power needs, the opportunities that exist for parallelism,
whether the algorithms line up nicely, and whether your application has access
to a Cell/B.E.-enabled library. This article is Part 1 of a 3-part series from
the IBM Redbook(R) "Programming the Cell Broadband Engine: Examples and Best
Practices." [09/10/08 update: Made various changes based on updates since the
IBM Redbook was published.--Ed.]
|
|
Articles |
|
10 Sep 2008 |
|
| |
Page has permanently moved...
This page has moved permanently.
|
|
Articles |
|
09 Sep 2008 |
|
| |
TechReview, Part 1: Discover the LAPACK library
For application programmers using the IBM Software Development
Kit for Multicore Acceleration (SDK), this article explains the basic
structure of the IBM Linear Algebra Package (LAPACK) library. The LAPACK is based on a
published standard interface for commonly used linear algebra operations in
high performance computing and other scientific domains.
|
|
Articles |
|
02 Sep 2008 |
|
| |
A close-up on SDK 3.0, Part 1: Rebuilding code from src.rpm
The Cell/B.E. SDK 3.0 includes several src.rpm packages that contain the
source code for some of the SDK libraries. This article describes
the steps needed to install the src.rpm, unpack the source into a
directory where it can be viewed and changed, and rebuild a new rpm.
|
|
Articles |
|
26 Aug 2008 |
|
| |
Core partners, Part 5: Increasing SPU performance with instruction scheduling
The collection of processors in a Cell Broadband Engine(TM) (Cell/B.E.) processor
displays a DSP-like architecture. This means that the order in which the SPUs
execute the instructions can have a significant effect on performance. Without a good scheduling
mechanism in place, data dependencies can stall processor performance. In
this article, learn from a Cmpware expert how and why to use the Cmpware
CMP-DK Cell/B.E. SPU Scheduling Tool, which permits fast and easy analysis
of SPU code in an intuitive, graphical format.
|
|
Articles |
|
19 Aug 2008 |
|
| |
Fun with DaCS, Part 1: Using an error handler
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to create and
register a user error handler for use with the Data Communication and
Synchronization library (DaCS). The "Data Communication and Synchronization Library for
Cell Broadband Engine Programmer’s Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
05 Aug 2008 |
|
| |
Complex networking using Linux on Power blades
Blades are an excellent choice for many applications and services,
especially in the telecommunications service provider industry. But the unique
requirements of these provider networks often require configurations that are
complex and need up-front focus and planning so all the stringent functional
requirements are met. In this article, learn how to plan and set up the
necessary network configurations for a POWER6 JS22 blade deployment.
|
|
Articles |
|
05 Aug 2008 |
|
| |
The little broadband engine that could: More on rendering fractals on the SPE
In the previous article in the series, you learned about the challenges
of rendering fractals on the SPE. That article focused on the SPEs copying their rendering results directly into the
target data buffer. This article shows you how the fractal generator can be
optimized further by taking advantage of the SPE's fondness for vector
operations.
|
|
Articles |
|
29 Jul 2008 |
|
| |
Fun with ALF, Part 6: Using task dependency
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task dependency in a two-stage pipeline
application. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
22 Jul 2008 |
|
| |
Cell/B.E. SDK: Code sample directory
In this article, you'll find tables indicating the locations of code
samples that illustrate how to use the IBM SDK for Multicore Acceleration.
This article will be updated with new code samples.
|
|
Articles |
|
15 Jul 2008 |
|
| |
BladeCenter QS: Maximizing memory performance
This article compares the CBEA processor memory access
model (with a focus on the IBM BladeCenter(R) QS21 and QS22) with that of general
purpose processors, providing programmer guidelines to ensure that
applications can be developed for maximum memory performance. This article also
describes how to use the Cell Performance Counter tool when
monitoring memory access activities for tuning and debugging memory
performance.
|
|
Articles |
|
01 Jul 2008 |
|
| |
Core partners, Part 4: Managing the PlayStation 3 Wi-Fi network
Terra Soft Solutions IT Manager Aaron Johnson shows you, step-by-step, how to configure and encrypt the built-in Wi-Fi network that comes with the
Cell Broadband Engine(TM)-based Sony PlayStation 3. And, as a little bonus, get 16 quick
steps that explain how to switch from a wireless network back to a wired network on the PS3.
|
|
Articles |
|
17 Jun 2008 |
|
| |
The little broadband engine that could: Rendering fractals on the SPE
In the previous article in the series, you learned some reasons why there
were no appreciable performance gains when you migrated the
fractal-rendering program from running on one SPE to running on multiple SPEs. This
article is going to illuminate the
challenge of rendering fractals on the SPE. The focus is on the SPEs copying their
rendering results directly into the target data buffer.
|
|
Articles |
|
10 Jun 2008 |
|
| |
Fun with ALF, Part 5: Using overlapped I/O buffers to add matrices
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) overlapped input-output buffers to perform
matrix addition. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
03 Jun 2008 |
|
| |
The little broadband engine that could: Looking at some DaCS performance fine-tuning issues
In the previous article in the series, you migrated a fractal-rendering program from earlier in the
series to run using the DaCS data library with no appreciable performance gains when
going from running on one SPE to running on multiple SPEs. This article explores ways to optimize
performance.
|
|
Articles |
|
20 May 2008 |
|
| |
Fun with ALF, Part 4: Determining the dot product of large vectors
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) bundled work block distribution and
the task context to manage situations in which the work block cannot hold the
partitioned data because of a local memory size limit. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
09 May 2008 |
|
| |
IBM BladeCenter QS21 hardware performance glossary
Although there is extensive published data about the hardware performance
features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a
multitude of applications ported to it), there is little on the specific hardware
performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two
Cell/B.E processors as well as an elaborate IO subsystem. This glossary goes with
the article "Evaluating IBM BladeCenter QS21 hardware performance."
In that article, the
authors close the performance gap by providing information about basic latencies, throughputs,
and relative execution times for some key computational benchmark kernels, such as
Linpack and SPEC2000. The article also delivers a basic architectural overview of
the system. And, you can get tips on how to optimize application
performance.
|
|
Articles |
|
06 May 2008 |
|
| |
Evaluating IBM BladeCenter QS21 hardware performance
Although there is extensive published data about the hardware performance
features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a
multitude of applications ported to it), there is little on the specific hardware
performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two
Cell/B.E processors as well as an elaborate IO subsystem. In this article, the
authors close that gap by providing information about basic latencies, throughputs,
and relative execution times for some key computational benchmark kernels, such as
Linpack and SPEC2000. The article also delivers a basic architectural overview of
the system. And, you can get tips on how to optimize application
performance.
|
|
Articles |
|
06 May 2008 |
|
| |
Fun with ALF, Part 3: Finding minimum and maximum values
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task context to keep the partial computing
results for each task instance and then combine them. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
29 Apr 2008 |
|
| |
The little broadband engine that could: DaCS--flexible and complex
In an earlier article in this series, the author introduced a fractal-generation
program built around the IDL interface that showcased the strength of IDL's
straightforward API. Executing the program was almost like calling a function and
getting results. In this article (and using the same basic program), the author
demonstrates the Data Communication and Synchronization library's (DaCS) greater
flexibility and the tradeoff: additional complexity. With DaCS, it's possible to pass the fractal pattern in as an initial argument,
then use buffers to pass data back and forth as they are processed. While this requires
more design work, but it might actually be more efficient. This article also shows that DaCS allows
for much more carefully tuned inputs and outputs.
|
|
Articles |
|
22 Apr 2008 |
|
| |
Cell/B.E. SDK 3.0 tools, Part 1: Using performance tools
This introductory tutorial, designed as a companion for the IBM SDK for
Multicore Acceleration, Version 3.0 (otherwise known as the Cell Broadband
Engine(R) SDK), teaches you how to use five performance tools that reside in the SDK
3.0: OProfile, Cell Performance Counter, Performance Debugging Tool, the PDT Trace
Reader, and FDPR-Pro. The Visual Performance Analyzer, available separately, is also highlighted.
|
|
Tutorials |
|
15 Apr 2008 |
|
| |
Core partners, Part 3: Transforming Gedae-built portable apps
This concise study examines the portability of
applications developed in Gedae by analyzing the work required to move an example
application from a simulation on a PC to actually running on a DSP board (the
Mercury Computer System AdapDev system) to running on a multicore Cell Broadband
Engine(TM) (Cell/B.E.). The article illustrates how architecture considerations were taken into account
when porting the application to each system. You can see the amount of work required to
port the application and the performance of the application on each system.
|
|
Articles |
|
08 Apr 2008 |
|
| |
Linux development on the PlayStation 3, Part 3: Slimming down X11 with tiny tools
The Sony PlayStation 3 (PS3) runs Linux, but getting it to run well requires
some tweaking. In the third and final article of this series on PS3 Linux, Peter
Seebach talks about ways to get X11 slimmed down to fit on a smaller memory budget.
|
|
Articles |
|
08 Apr 2008 |
|
| |
Linux development on the PlayStation 3, Part 2: Working with memory
The Sony PlayStation 3 (PS3) runs Linux, but getting it to run well requires
some tweaking. In this article, the second in a series, Peter Seebach takes a look
at where all the memory goes and how to reclaim it.
|
|
Articles |
|
31 Mar 2008 |
|
| |
Fun with ALF, Part 2: Converting I/O data
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task context buffer as a large lookup table to
convert the 16-bit input data to 8-bit output data. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
25 Mar 2008 |
|
| |
Fun with ALF, Part 1: Adding large matrices together
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) in the IBM SDK for Multicore Acceleration 3.0 to
add two large matrices together. There is one example for host data
partitioning and one for accelerator data partitioning. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content.
|
|
Articles |
|
18 Mar 2008 |
|
| |
Linux development on the PlayStation 3, Part 1: More than a toy
The Sony PlayStation 3 (PS3) runs Linux, but getting it to run well requires
some tweaking. In this article, first in a series, Peter Seebach introduces the
features and benefits of PS3 Linux, and explains some of the issues that might
benefit from a bit of tweaking.
|
|
Articles |
|
18 Mar 2008 |
|
| |
The little broadband engine that could: IDL is dead--long live DaCS!
In SDK 3.0, the Data Communication and Synchronization library (DaCS)
provides a sparkling substitute for IDL. DaCS is a set of services to aid the development
of applications and application frameworks in a heterogeneous multi-tiered system.
This article takes you on a tour of the DaCS process model and
explores general DaCS principles, including communication and memory access.
|
|
Articles |
|
04 Mar 2008 |
|
| |
The little broadband engine that could: Reviewing the newest little SDK that installs natively on PS3
Come along on a little train tour of the SDK for Multicore Acceleration 3.0
to see what's different for developers and how you can make good use of the SDK,
including native installation on PS3, support for FC7 and RHEL 5.1, enhanced compilers,
Fortran and Ada support, BLAS, ALF, and DaCS--oh my!
|
|
Articles |
|
19 Feb 2008 |
|
| |
New to Cell/B.E., multicore, and Power Architecture technology
The Multicore acceleration technology zone on developerWorks contains
articles, tutorials, and tips to help developers with Cell Broadband
Engine(TM), multicore, and Power Architecture(TM) application development,
optimization, and migration. For users trying to find their way in a new
topic, all of that information can be overwhelming. This page provides an
overview for readers who would like to learn about this technology but don't
know where to start.
|
|
|
|
12 Feb 2008 |
|
| |
Core partners, Part 2: Using DDT to clean up Cell/B.E. app bugs
Allinea Software's Distributed Debugging Tool (DDT)
provides an easy-to-use, capable debugger that is able to debug complete Cell
Broadband Engine applications, including multiple threads within a single Cell/B.E.
processor and clusters of Cell/B.E. processors.
|
|
Articles |
|
05 Feb 2008 |
|
| |
Cell/B.E. container virtualization, Part 2: Implementation issues
This three-part series illustrates a
hardware-resource-focused form of software virtualization known as container
virtualization (or operating system virtualization), demonstrated through the open
source project OpenVZ. The series provides a comprehensive overview of all the
components and techniques needed to virtualize the Cell/B.E. processor with software
methods. This second article of the series details the implementation of
dedicated virtualization and partitioning that was described in Part 1 of the series.
|
|
Articles |
|
08 Jan 2008 |
|
| |
Cell/B.E. container virtualization, Part 1: Concepts, architectures, and tools
This three-part series illustrates a
hardware-resource-focused form of software virtualization known as container
virtualization (or operating system virtualization), demonstrated through the open
source project OpenVZ. The series provides a comprehensive overview of all the
components and techniques needed to virtualize the Cell/B.E. processor with software
methods. This first article of the series discusses the basic concepts
involved, illustrates the salient points of the OpenVZ and Cell/B.E. architectures
and how they work together, and describes some of the OpenVZ tools.
|
|
Articles |
|
11 Dec 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 1: Create an SPU project
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences.
|
|
Tutorials |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 6: Use simulator consoles, use the ALF wizard, and set IDE preferences
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences.
|
|
Tutorials |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 5: Debug and complete dynamic or static performance
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences.
|
|
Tutorials |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 4: Configure the application launcher
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences.
|
|
Tutorials |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 3: Create the Cell/B.E. simulator environment
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences.
|
|
Tutorials |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 2: Create a PPU project
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences.
|
|
Tutorials |
|
13 Nov 2007 |
|
| |
Porting workshop, Part 7: Getting the most performance
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In part seven, the authors evaluate the performance data to date.
|
|
Articles |
|
06 Nov 2007 |
|
| |
Cell/B.E.
SDK: Understanding the terminology
A quick-reference glossary of terms you might encounter when installing and
using the Cell Broadband Engine (Cell/B.E.) processor
SDK.
|
|
Articles |
|
19 Oct 2007 |
|
| |
Porting workshop, Part 6: Tying it all together
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In this Part 6, the authors provide a summary of what the series has
covered so far.
|
|
Articles |
|
16 Oct 2007 |
|
| |
Minimize recoding impact, Part 2: Removing obstacles to speedy performance
The first article in the series describes how to do a basic port to the Cell Broadband Engine process. This
second article goes further in hammering out the details, including removing limitations
based on DMA-transfer size, partitioning the program across multiple SPEs, and
improving the program's speed even more.
|
|
Articles |
|
16 Oct 2007 |
|
| |
PS3 fab-to-lab, Part 2: Generating and analyzing signals
How do you take the Cell Broadband Engine (Cell/B.E.) processor from an
off-the-shelf Sony PLAYSTATION 3 (PS3) and use it to construct a piece of
Linux(R)-based laboratory equipment (in essence, take the Cell/B.E. from fab to hab
to lab)? In this series, Lewin Edwards shows you how to go from game console to
simple audio-bandwidth spectrum analyzer and function generator. In this article,
the author shows you how to build on the infrastructure from Part 1 to make the
system into a fully operational, if primitive, spectrum analyzer.
|
|
Articles |
|
02 Oct 2007 |
|
| |
Porting workshop, Part 5: Mixed-precision workloads
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In this Part 5, the authors determine how to make mixed-precision
calculations work with the sample application.
|
|
Articles |
|
02 Oct 2007 |
|
| |
IBM Installation Toolkit: Loading Linux on POWER
The IBM Installation Toolkit for Linux on POWER simplifies the installation of Linux on
virtualized and non-virtualized Power machines, gives you a bootable rescue DVD, and
provides the software needed to fully exploit the Power platform. Learn to use the
toolkit to install Red Hat Enterprise Linux and SUSE Linux Enterprise Server on
IBM System p and System
i5 machines.
|
|
Articles |
|
26 Sep 2007 |
|
| |
The little broadband engine that could: Use multiple SPEs for a single task
Peter Seebach uses a simple, iterative-function fractal generator program to describe how to use multiple
Synergistic Processor Engines (SPEs) to vectorize a single task using the job queue model.
|
|
Articles |
|
18 Sep 2007 |
|
| |
Porting workshop, Part 4: Mersenne-Twister
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In this Part 4, the authors explore the Mersenne-Twister random-number
generator to determine its effect.
|
|
Articles |
|
18 Sep 2007 |
|
| |
Porting workshop, Part 3: Initial performance results
The seven, quick-read parts of this series, "Porting workshop," take you on a real-world trip from strategy and planning through workload execution through performance tweaking through optimization to a solid conclusion -- how to most effectively port compute-intensive applications to the Cell Broadband Engine platform. In part three, the authors run and review performance tests and data on the modified code.
|
|
Articles |
|
04 Sep 2007 |
|
| |
Minimize recoding impact, Part 1: How to make an SPE and existing code work together
Traditional porting requires identifying and abstracting out the
architecture-dependent code: making code endian-independent, working through minor
API differences, and including the appropriate header files and libraries. While
this procedure works for getting code to run on the Cell Broadband Engine
(Cell/B.E.) processor, to actually use the extra processing elements, you have to
put in extra work, including reworking the code and rethinking the build process. In
this series, learn to take advantage of the Synergistic
Processor Elements (SPEs) in existing code and only make a minimal impact to the existing code and build process.
|
|
Articles |
|
04 Sep 2007 |
|
| |
Porting workshop, Part 1: Processor porting strategies
The seven, quick-read parts of this series, "Porting workshop," take you on
a real-world trip from strategy and planning through workload execution through
performance tweaking through optimization to a solid conclusion -- how to most
effectively port compute-intensive applications to the Cell Broadband Engine
platform. In part one, discover the top three strategies for porting.
|
|
Articles |
|
07 Aug 2007 |
|
| |
Porting workshop, Part 2: Original code analysis
The seven, quick-read parts of this series, "Porting workshop," take you on a real-world trip from strategy and planning through workload execution through performance tweaking through optimization to a solid conclusion -- how to most effectively port compute-intensive applications to the Cell Broadband Engine platform. In part two, explore the original code with Linux profiling tools.
|
|
Articles |
|
07 Aug 2007 |
|
| |
The little broadband engine that could: Why is my scalar code so slow?
The SIMD-only architecture of the Cell Broadband Engine (Cell/B.E.)
processor's Synergistic Processor Engine (SPE) is an architecture that has no scalar
operations -- all operations are performed on 16-byte vectors. Design code that helps
the Cell/B.E. compiler make efficient use of this architecture.
|
|
Articles |
|
07 Aug 2007 |
|
| |
Changes in libspe: How libspe2 affects Cell Broadband Engine programming
The standard library that Power Processor Element (PPE) programs use to
access and manage Synergistic Processor Elements (SPEs), called
libspe, has undergone a major revision. The Cell Broadband Engine (Cell/B.E.)
SDK 2.1 officially changes the library interface from libspe1 to libspe2. In
this article, Jonathan Bartlett introduces the libspe2 concepts and shows how to do basic SPE process management and communication with libspe2.
|
|
Articles |
|
17 Jul 2007 |
|
| |
The little broadband engine that could: Mailboxes and interrupts
Meet two more means of communication between the SPE and the PPE -- mailboxes
and signal notification. Mailboxes are special-purpose registers, similar to the I/O
registers used to communicate with peripheral devices on some systems, available on the SPEs and the PPE. Signal notification registers are registers which can be read or written to by the PPE, but which the SPE can only read.
|
|
Articles |
|
03 Jul 2007 |
|
| |
Porting practices: Compute-intensive applications
The Cell Broadband
Engine (Cell/B.E.) processor has powerful computation capabilities, but to fully
unleash its power, you need to provide a unique programming paradigm. In this article,
learn best practices for porting a JPEG compression application to the Cell/B.E.
Synergistic Processor Engine (SPE), and see how to take advantage of the processor's unique architecture and avoid its shortcomings.
|
|
Articles |
|
19 Jun 2007 |
|
| |
The little broadband engine that could: An introduction to using SPEs for Cell Broadband Engine development
In this first article in a series on Cell Broadband Engine (Cell/B.E.) development, Peter
Seebach introduces the API used to run programs on SPEs, focusing specifically on
loading code on an SPE and sending data to it for processing.
|
|
Articles |
|
05 Jun 2007 |
|
| |
Tech tips: Ten helpful tips when building SPE applications in C
These ten tips can save you
a lot of trouble when you're coding your C applications for the Cell Broadband
Engine (Cell/B.E.) SPU.
|
|
Articles |
|
05 Jun 2007 |
|
| |
PS3 fab-to-lab, Part 1: Build Linux lab equipment from a Sony PLAYSTATION 3
How do you take the Cell Broadband Engine (Cell/B.E.) processor from an
off-the-shelf Sony PLAYSTATION 3 (PS3) and use it to construct a piece of
Linux-based laboratory equipment (in essence, taking the Cell/B.E. from fab to hab
to lab)? In this series, Lewin Edwards shows you how to go from game console to
simple audio-bandwidth spectrum analyzer and function generator. First up, uncover
the design intent of the project and then make a close inspection of the details of
the user interface implementation as you start a journey to generate and analyze
signals on the Cell/B.E. processor.
|
|
Articles |
|
15 May 2007 |
|
| |
Core partners, Part 1: Build high-performance apps for multicore processors
The RapidMind Development Platform provides a simple single-source mechanism to develop portable high-performance applications for multicore processors. In particular, you can use it to develop applications that fully exploit the power of the Cell Broadband Engine (Cell/B.E.) processor's unique architecture by writing only one, single-threaded C++ program using an existing C++ compiler. In this article, author Michael McCool takes you on a guided tour of the RapidMind Development Platform.
|
|
Articles |
|
01 May 2007 |
|
| |
Tech tips: SPU vector intrinsics at your fingertips
Know these common C/C++ language extensions intrinsics and greatly simplify the arduous task of using the SPU's assembly language.
|
|
Articles |
|
01 May 2007 |
|
| |
SoC drawer: The Cell Broadband Engine chip: High-speed offload for the masses
Cell Broadband Engine (Cell/B.E.) chips are leading the broadband revolution in computing and provide the core silicon DNA for supercomputing, medical image processing, and many emergent applications, as worldwide connectivity and bandwidth continue to change the world we live in. This article explores the performance of application code on the Sony PLAYSTATION 3's Cell Broadband Engine system running Yellow Dog Linux. A simple program demonstrates how multithreaded applications that use the Synergistic Processing Elements to offload work can enjoy tremendous speedup.
|
|
Articles |
|
17 Apr 2007 |
|
| |
Cell/B.E. SDK 2.1: Setting up Fedora Core 6
Before you can install and use the Cell Broadband Engine (Cell/B.E.) processor SDK Version 2.1, you need to get Fedora Core 6 up and running. Here's how.
|
|
Articles |
|
17 Apr 2007 |
|
| |
Massively multiplayer online games, Part 1: A performance-based approach to sizing infrastructure
Massively multiplayer online games (MMOGs) are some of the most complicated software systems under development today, often requiring dozens of developers, hundreds of artists, and truly massive infrastructures. This article is the first in a series of articles that will shine a light on the systems, storage, and networks needed to run an MMOG. It provides an introduction to MMOGs and demonstrates one approach to sizing a game's infrastructure. Learn how to figure out how much infrastructure you might need, as well as how to operate an MMOG.
|
|
Articles |
|
10 Apr 2007 |
|
| |
IBM microNews
06 April 2007
|
|
|
|
06 Apr 2007 |
|
| |
IBM microNews
06 April 2007
|
|
|
|
06 Apr 2007 |
|
| |
The Power Architecture Time Base register in 64-bit Linux
Use the Power Architecture technology's Time Base register to measure time at the nanosecond level in Linux on PowerPC and Cell Broadband Engine (Cell/B.E.) microprocessors. Applications where this is useful include timestamping transactions (typically encrypted or digitally signed single-use messages), profiling code, and implementing small, precise software delays.
|
|
Articles |
|
04 Apr 2007 |
|
| |
Programming high-performance applications on the Cell/B.E. processor, Part 6: Smart buffer management with DMA transfers
Explore the concepts of double-buffering and multibuffering to improve code speed by parallelizing processing and data transfer, and allowing the SPE's memory flow controller (MFC) to coordinate the best order of operations for loading and storing.
|
|
Articles |
|
03 Apr 2007 |
|
| |
An introduction to the IDE for the Cell Broadband Engine SDK
This introductory walk-through, updated for the Cell Broadband Engine (Cell BE) SDK V2.1, explores the Cell BE processor IDE and offers a click-for-click lesson on how to construct a simple project.
|
|
Tutorials |
|
30 Mar 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 5: Programming the SPU in C/C++
In Part 5 of the "Programming high-performance applications on the Cell BE processor" series, apply
your knowledge of the synergistic processing unit (SPU) to programming the Cell Broadband Engine (Cell BE) processor in C/C++. Learn how to use the vector extensions, direct the compiler to do branch prediction, and perform DMA transfers in C/C++.
|
|
Articles |
|
20 Mar 2007 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 4: The battle to make the virtual cabinets work
Nothing is as easy as one might hope. Since the last article was posted, the Heath Robinson Rube Goldberg (HRRG) Computer team has been battling every step of the way to bring the HRRG emulator's virtual cabinets online. On the way, we've re-engineered everything several times, and run across some unanticipated scenarios...
|
|
Articles |
|
20 Mar 2007 |
|
| |
IBM microNews
09 March 2007
|
|
|
|
09 Mar 2007 |
|
| |
IBM microNews
23 March 2007
|
|
|
|
09 Mar 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 4: Program the SPU for performance
Write optimal code for the Cell Broadband Engine (Cell BE) processor's synergistic processing unit (SPU) and have your programs running lightning fast. This installment of "Programming high-performance applications on the Cell BE processor" covers SIMD vector programming, branch elimination, loop unrolling, instruction scheduling, and branch hinting techniques. Previous installments have covered the basics of the Sony PLAYSTATION 3, the Cell BE architecture, and SPU programming.
|
|
Articles |
|
06 Mar 2007 |
|
| |
Assembly language for Power Architecture, Part 4: Function calls and the PowerPC 64-bit ABI
The ABI, or Application Binary Interface, is the set of conventions that allow
programs written in different languages or compiled by different compilers to call each
other's functions. This article, the last in a four-part series, discusses the
PowerPC ABI for 64-bit ELF (UNIX-like) systems and how to write and call functions using it.
Knowing in detail how the 64-bit PowerPC ABI works will help you write 64-bit programs
for the POWER5 and other PowerPC-based processors more effectively, whether you program
in assembly language or not. There is also a 32-bit ABI that is not covered in this article.
|
|
Articles |
|
28 Feb 2007 |
|
| |
IBM microNews
23 February 2007
|
|
|
|
23 Feb 2007 |
|
| |
Xilinx hijinx, Part 2: Building and loading bitstreams and PowerPC code
Explore both the hardware and software sides of a complete Virtex4 project. In this second and final installment of the Xilinx hijinx series, you add and remove device cores from your project, interconnect project components, build the bitstream, integrate it with C code, and download the entire thing to the FPGA.
|
|
Articles |
|
22 Feb 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 3: Meet the synergistic processing unit
Continue looking in depth at the Cell Broadband Engine (Cell BE) processor's synergistic processor elements (SPEs) and how they work at the lowest level. This installment explores storage alignment issues and the communication facilities of the SPEs.
|
|
Articles |
|
22 Feb 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 2: Program the synergistic processing elements of the Sony PLAYSTATION 3
Take even greater advantage of the synergistic processing elements (SPEs) of the Sony PLAYSTATION 3 (PS3) in this installment of "Programming high-performance applications on the Cell BE processor." Part 1 showed how to install Linux on the PS3 and explored a short example program. Part 2 looks in depth at the Cell Broadband Engine processor's SPEs and how they work at the lowest level.
|
|
Articles |
|
07 Feb 2007 |
|
| |
Xilinx hijinx, Part 1: The ML403 out-of-box experience
Discover reasons you might choose an FPGA-based system over a traditional hard-IP microcontroller, and identify the learning curve traditional programmers face when meeting RAM-based programmable logic for the first time. In this new series, Lewin Edwards unpacks the Xilinx ML403 Embedded Development Kit and sorts out some of its idiosyncrasies.
|
|
Articles |
|
30 Jan 2007 |
|
| |
Assembly language for Power Architecture, Part 3: Programming with the PowerPC branch processor
The last two articles discussed the outline of how programs on the POWER5 processor work using the 64-bit PowerPC instruction set, how the PowerPC instruction set addresses memory, and how to do position-independent code. This article focuses on the very powerful condition and branch instructions available in the PowerPC instruction set.
|
|
Articles |
|
17 Jan 2007 |
|
| |
SoC drawer: SoCs and the digital content revolution
SoC (system-on-a-chip) architectures could significantly accelerate digital video processing and enable the digital video revolution. Sam Siewert offers an overview of digital video processing and emergent applications in the video realm and shows how SoCs can uniquely accelerate processing. If you're an SoC architect, developer, Power Architecture platform software developer, or anyone creating digital video applications and services, this article is for you.
|
|
Articles |
|
17 Jan 2007 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 3: Introducing the HRRG emulator
The continuing effort to add at least one series of (vacuum) tubes to the Internet progresses with an introduction to the workings of and thinking behind the Heath Robinson Rube Goldberg (HRRG) emulator. And stay tuned because next time you'll get to download it.
|
|
Articles |
|
10 Jan 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 1: An introduction to Linux on the PLAYSTATION 3
The Sony PLAYSTATION 3 (PS3) is the easiest and cheapest way for programmers to get their hands on the new Cell Broadband Engine (Cell BE) processor and take it for a drive. Discover what the fuss is all about, how to install Linux on the PS3, and how to get started developing for the Cell BE processor on the PS3.
|
|
Articles |
|
03 Jan 2007 |
|
| |
Assembly language for Power Architecture, Part 2: The art of loading and storing on PowerPC
The previous article in this series introduced assembly language programming
using the 64-bit PowerPC instruction set on POWER5 and other processors that use
these instructions. This article drills down and discusses the specifics of 64-bit
PowerPC assembly language programming on Linux and UNIX-like operating systems,
focusing on data access methods and position-independent code.
|
|
Articles |
|
29 Nov 2006 |
|
| |
Tuning the CPC945 memory controller
|
|
Articles |
|
21 Nov 2006 |
|
| |
Don't let these disasters happen to you: A pox on modern engineering, Part 2
While per-transistor failure rates may be down, overall reliability hasn't declined as much as people sometimes assume, and modern systems are often much harder to repair than older ones. Following up on a previous article, Lewin Edwards reviews more of the problems modern engineers face.
|
|
Articles |
|
14 Nov 2006 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 2: Partitioning the system
In Part 2 of the Heath Robinson Rube Goldberg (HRRG) Computer series, learn how to partition the system, trading off between implementation complexity, granularity, and flexibility, while also
minimizing the bandwidth required to communicate among the various modules.
|
|
Articles |
|
08 Nov 2006 |
|
| |
Directions: IBM and partners open up the silicon supply chain with the Common Platform
Steve Longoria, IBM vice president of Semiconductor Platforms, discusses the collaboration among IBM, Chartered, and Samsung in the open Common Platform technology initiative, and how the move is shaking up the industry's traditional closed model.
|
|
Articles |
|
26 Oct 2006 |
|
| |
Don't let these disasters happen to you: A pox on modern engineering, Part 1
Between IP litigation and ever greater demands for "baseline" functionality that requires licensing, developing new products has become a treacherous minefield for engineers to navigate. In this article, Lewin Edwards outlines some of the dangers which are making it harder for engineers to just get out there and build something.
|
|
Articles |
|
17 Oct 2006 |
|
| |
SoC drawer: Eyes inside the silicon
Author Sam Siewert describes basic methods and tools that can provide eyes into the silicon for architects, designers, and engineers working with reconfigurable systems-on-chips (SoCs). SoCs like the Xilinx Virtex line provide a hybrid platform for hardware and software co-design and implementation of real-time services and digital signal processing. Hybrid SoCs employing Power Architecture technology-based software interfacing to highly customized hardware state machines can help designers unlock the power of application-specific hardware acceleration. The integration of the Power Architecture cores with reconfigurable logic provides a powerful prototyping and product platform for SoCs. This power can be better unleashed using trace, debug, and analysis tools to visualize and tune hardware and software interfaces and interaction.
|
|
Articles |
|
10 Oct 2006 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 1: Implementing a computer using a mixture of technologies from relays to fluidic logic
Imagine a computer formed from a mixture of technologies ranging from relays to fluidic logic. Now imagine being able to create a single piece of such a computer (perhaps as small as a single word of memory) in the technology of your choice, and then using the Internet to run your masterpiece in conjunction with other portions of the system created by contributors located around the world! Author Clive (Max) Maxfield explains the creation of just such a computing engine and how you can be involved.
|
|
Articles |
|
03 Oct 2006 |
|
| |
Assembly language for Power Architecture, Part 1: Programming concepts and beginning PowerPC instructions
The POWER5 processor is a 64-bit workhorse used in a variety of settings. Starting with this introduction to assembly language concepts and the PowerPC instruction set, this series of articles introduces assembly language in general and specifically assembly language programming for the POWER5.
|
|
Articles |
|
03 Oct 2006 |
|
| |
Linux on board: Inside the MediaMVP
As an MP3 and MPEG player, the Hauppauge MediaMVP lets you play digital media through your television set. As a tightly purposed embedded device, it is an excellent example of a compact Linux implementation on minimal hardware.
|
|
Articles |
|
28 Sep 2006 |
|
| |
Taking OpenPower for a spin, Part 1: Exploring 64-bit development on POWER5
The OpenPower program offers free remote access to servers running 64-bit Linux on POWER5 processors. In Part 1 of the Taking OpenPower for a spin series, author Peter Seebach introduces the process of getting access to a system and compiling applications for it, both as 32-bit and 64-bit applications. He pays particular attention to issues unique to "guest" software development without root privileges -- something most Linux users have never had to do.
|
|
Articles |
|
26 Sep 2006 |
|
| |
Taking OpenPower for a spin, Part 3: How to avoid having to port your code
Why is porting even hard? In this last article of the "Taking OpenPower for a spin" series, Peter Seebach looks at what kinds of issues are involved with portability from one architecture to another and contrasts APIs with hardware interfaces.
|
|
Articles |
|
26 Sep 2006 |
|
| |
Taking OpenPower for a spin, Part 2: Porting issues in targeting 64-bit systems
In Part 2 of the Taking OpenPower for a spin series, Peter Seebach reviews code portability issues when porting to 64-bit systems, looking in particular at code and data portability, with concrete examples of some of the rare kinds of code that require real modification.
|
|
Articles |
|
26 Sep 2006 |
|
| |
Testing and measuring the TAMS 3011, Part 6: Booting NetBSD on new hardware, the saga begins
Porting an operating system to new hardware can be a fairly easy process, or a fairly difficult one, depending on the issues you encounter. Peter Seebach walks you through his experience getting NetBSD running on a new board using existing hardware.
|
|
Articles |
|
19 Sep 2006 |
|
| |
Standards and specs: XML: Half a standard is better than none
A pervasive misconception common today is that simply designing your file format around XML somehow makes it magically portable, extensible, and intelligible by other programs. Peter Seebach explains why using XML is only part of the story when you're designing an extensible file format.
|
|
Articles |
|
12 Sep 2006 |
|
| |
Don't let these disasters happen to you: Five more engineering hints you'll rarely hear
Lewin Edwards presents five more engineering tips, this time aimed at smaller companies without the overhead, or support structures, of a larger organization.
|
|
Articles |
|
05 Sep 2006 |
|
| |
Multifunction multimedia machine, Part 5: Remote control is the new local interface
Add a Web-based user interface to a previously developed multimedia client in this episode of the Multifunction multimedia machine series. Author Lewin Edwards looks both at user-interface and back-end design issues, and shows how local browser functionality is an interesting alternative to requiring a remote browser.
|
|
Articles |
|
29 Aug 2006 |
|
| |
SoC drawer: SoC design for hardware acceleration, Part 2
In the SoC design for hardware acceleration series, author Sam Siewert migrates a simple C function to a SystemC specification that can be simulated and verified for ultimate implementation as a hardware function. Part 1 provided the C code and a general overview of video capture, streaming, and processing. Part 2 shows how hardware acceleration of emergent applications, such as video streaming, can benefit from system-on-chip (SoC) design and reconfigurable SoCs with hybrid C software and field-programmable gate array (FPGA)-based functionality.
|
|
Articles |
|
22 Aug 2006 |
|
| |
Standards and specs: Of RoHS and rushed standards
When the ex cathedra RoHS Directive came down, it was missing a
little crucial piece of information -- how manufacturers, distributors, and purchasers of parts could communicate to each other the RoHS status of every part.
|
|
Articles |
|
15 Aug 2006 |
|
| |
Debugging Cell Broadband Engine systems
Software development for new architectures can be an intimidating prospect, but the Cell Broadband Engine (Cell BE) SDK 1.1 provides the debugging tools you need to tackle it for the Cell BE architecture. This article describes how to use new versions of the GNU Debugger (GDB) to diagnose problems in both PPU and SPU programs.
|
|
Articles |
|
08 Aug 2006 |
|
| |
Don't let these disasters happen to you: The top five engineering hints you'll rarely hear
Lewin Edwards presents five engineering tips that are crucially important to successful product engineering, but which are rarely brought up in discussions of engineering practices.
|
|
Articles |
|
01 Aug 2006 |
|
| |
Power Architecture directions: IBM Design Consulting teams and "collaborative innovation"
Lee Green, vice president, IBM Brand Values and Experience, discusses how the IBM Design Consulting Services (DCS) group came into being, how it works in virtual
teams with clients and other IBM customer and technical service groups, some innovative products resulting from this design collaboration, and how DCS helps IBM penetrate new markets.
|
|
Articles |
|
01 Aug 2006 |
|
| |
Partition management with EWLM, Part 1: The basic rules
You've gathered performance data with the help of the IBM Enterprise Workload Manager (EWLM) -- now you're ready to exploit this data by enabling intelligent partition management of your AIX and Linux partitions running on IBM System p5 servers. In this first part of a two-part series, you get an introduction to logical partitioning. You're guided through the steps to set up your environment for EWLM partition management, and learn how to configure partitions.
|
|
Articles |
|
25 Jul 2006 |
|
| |
Power Architecture directions: Brand-new brand for Power Architecture technology
Michael E. Sullivan of IBM discusses how Power Architecture technology is being reborn under Power.org as a community-driven architecture and brand inspired by the open-source Linux model. Learn what motivated the changes, what they will mean for customers and partners, and what the new logo symbolizes.
|
|
Articles |
|
24 Jul 2006 |
|
| |
Partition management with EWLM, Part 2: Partition management in action
You've gathered performance data with the help of the IBM Enterprise Workload Manager -- now you're ready to exploit this data by enabling intelligent partition management of your AIX and Linux partitions running on IBM System p5 servers. Jump into the action by examining the topology of this test environment and the workload used, looking at the domain policy. Then, run the workload and observe the partition management actions taken by EWLM.
|
|
Articles |
|
18 Jul 2006 |
|
| |
Page has permanently moved...
This information has been updated for Version 2.0 of the Cell Broadband Engine SDK and is now superseded by two documents, which you can access from the links below. We apologize for any inconvenience.
|
|
|
|
12 Jul 2006 |
|
| |
Page has permanently moved...
This information has been updated for Version 2.0 of the Cell Broadband Engine SDK and is now superseded by two documents, which you can access from the links below. We apologize for any inconvenience.
|
|
|
|
12 Jul 2006 |
|
| |
Page has permanently moved...
This information has been updated for Version 2.0 of the Cell Broadband Engine SDK and is now superseded by two documents, which you can access from the links below. We apologize for any inconvenience.
|
|
|
|
12 Jul 2006 |
|
| |
Maximizing the power of the Cell Broadband Engine processor: 25 tips to optimal application performance
Unlike on conventional processors, you can achieve near
theoretical-maximum performance for real applications on the Cell Broadband
Engine (Cell/B.E.) processor. For this, you must be aware of the Cell/B.E. processor's architectural characteristics: get to know them better with these 25 tips to optimal application
performance.
|
|
Articles |
|
27 Jun 2006 |
|
| |
Standards and specs: The Interchange File Format (IFF)
The IFF file format had many of the features still sought today in modern file formats. This month's Standards and specs looks at the IFF file format and the lessons it has for modern file formats, such as XML.
|
|
Articles |
|
13 Jun 2006 |
|
| |
Testing and measuring the TAMS 3011, Part 5: Porting NetBSD to the TAMS 3011
Having looked at Linux and eCos support for the TAMS 3011 in the previous installments, Peter Seebach examines NetBSD support for it, which turns out to entail a certain amount of coding.
|
|
Articles |
|
13 Jun 2006 |
|
| |
SoC drawer: SoC design for hardware acceleration, Part 1
System-on-chip (SoC) designs offer the opportunity to migrate functionality initially implemented in software and firmware into hardware acceleration engines and state machines. Reconfigurable SoCs based on processors in FPGA fabric, such as the PowerPC 405 in the Xilinx Virtex-4, provide a platform for rapid migration of functionality from PowerPC software and firmware to the FPGA logic. Configurable application-specific integrated circuit (ASIC) SoCs can be optimized similarly over product revisions as SoC ASIC roadmap configurations are defined. This article examines methods for software design, specification, and implementation that will simplify future efforts to offload software functionality to hardware. Basic video and image processing algorithms provide working example algorithms for this article and the next.
|
|
Articles |
|
06 Jun 2006 |
|
| |
Testing and measuring the TAMS 3011, Part 4: Interfacing with flash and avoiding file systems
The Z-machine interpreter is a benchmark for OS functionality and development environments. With the groundwork of porting curses accomplished in Part 3, this article shows you how to complete the Z-machine interpreter, setting it up to use flash memory to save state, without the newfangled luxury of a file system.
|
|
Articles |
|
30 May 2006 |
|
| |
Initializing memory efficiently on Power Architecture platforms
Learn to efficiently initialize memory on Power Architecture systems. Software Developer Carlos Cavanna compares simple loops clearing one byte at a time to more elaborate algorithms, including the DCBZ instruction to zero whole cache lines at a time. The article concludes with some rough performance numbers to help you tune your own applications.
|
|
Articles |
|
23 May 2006 |
|
| |
Standards and specs: Lies, statistics, and benchmarks
Benchmarks can be an excellent tool for predicting performance and estimating requirements. They can also be misleading, possibly catastrophically so. Benchmark standardization helps distinguish between a good estimate and a meaningless number.
|
|
Articles |
|
23 May 2006 |
|
| |
Building SOA applications with reusable assets, Part 2: SOA recipe reference example
This series explores how reusable assets, recipes and software patterns can facilitate the development of SOA solutions. This second article describes a reference example in which a recipe can be applied. Future articles will show how to apply SOA patterns to this reference example to satisfy non-functional requirements.
|
|
Articles |
|
23 May 2006 |
|
| |
Meet the experts: Peng Wu and Alex Eichenberger on compilers and hardware constraints
Programming in high-level languages such as C is like crossing an ocean without spending time looking at the water. developerWorks spent an hour with two IBM Research Compiler programmers exploring the ecosystem that lies beneath the surface.
|
|
Articles |
|
10 May 2006 |
|
| |
SoC drawer: SoC prognostication
Since its emergence about a decade ago, the SoC (system-on-a-chip) architecture has become the underlying architecture for many embedded systems and scalable supercomputers and is starting to find its way into general purpose computing as well. The SoC embodies what many believe to be the ultimate level of integration: an entire system on one chip. Moore's law and higher levels of integration made the SoC inevitable, but can this continue? And what's next? This article takes a step back to gain perspective on the SoC and to see where it is going in the future. Perhaps the more important question is: where should the highest level of integration be, and what will it enable 25 years from today?
|
|
Articles |
|
05 May 2006 |
|
| |
Everything you ever wanted to know about C types, Part 4: Portability and pitfalls
Effectively use the C type system, with help from Peter Seebach, as he covers Hungarian notation (the good kind and the bad kind), using typedef, portability issues, and major pitfalls.
|
|
Articles |
|
02 May 2006 |
|
| |
Cell Broadband Engine processor DMA engines, Part 2: From an SPE point of view
The Cell Broadband Engine (Cell BE) architecture provides on-chip DMA capabilities between the PPE and the SPEs. Meet the SPE interface to the DMA capabilities of the processor, from channel allocation to communication.
|
|
Articles |
|
02 May 2006 |
|
| |
CPI analysis on POWER5, Part 2: Introducing the CPI breakdown model
Make substantial improvements in performance analysis with a CPI analysis model built on the tools introduced in Part 1. Learn ways to analyze the specific performance counter data produced by profiling runs to obtain statistics for events which the CPU cannot directly report on.
|
|
Articles |
|
25 Apr 2006 |
|
| |
Standards and specs: Chip interconnects: When 133 MBps is too slow
New interconnect protocols and standards offer a variety of options in price and performance. Peter Seebach looks at four new protocols and ponders why we have more than one.
|
|
Articles |
|
24 Apr 2006 |
|
| |
The Cell Broadband Engine processor security architecture
The unrelenting evolution toward an even more open and connected computing infrastructure requires robust security to thrive. Learn how the Cell Broadband Engine processor's security architecture is uniquely suited for the challenges of this digital future.
|
|
Articles |
|
24 Apr 2006 |
|
| |
Five minutes with: Mark Nutter and Max Aguilar on the Cell BE memory model
The Power Architecture PowerPC core and the Cell Broadband Engine (Cell BE) PPE unit: how different are they? Find out why there is "nothing to fear" from Cell BE programming, after all.
|
|
Articles |
|
18 Apr 2006 |
|
| |
SPU pipeline examination in the IBM Full-System Simulator for the Cell Broadband Engine processor
Find out the exact cycle where the SPE stalls, or identify a poor choice of branch predictions, using pipeline tracing in the Cell Broadband Engine (Cell BE) simulator.
|
|
Articles |
|
17 Apr 2006 |
|
| |
CPI analysis on POWER5, Part 1: Tools for measuring performance
This article begins a short series on workload performance analysis on Power Architecture systems. Part 1 introduces the CPU feature set and a variety of useful tools for collecting data.
|
|
Articles |
|
04 Apr 2006 |
|
| |
Tuning the CPC925 memory controller
Give your development on the PowerPC 970 board a stable foundation by tuning the IBM CPC925 memory controller to match your board's analog characteristics. Author Neil Leeder gives step-by-step instructions on tuning the IBM CPC925 North Bridge chip for different memory configurations and selecting a middle-of-the-road parameter set to cope with different user-installable memory amounts and configurations.
|
|
Articles |
|
28 Mar 2006 |
|
| |
Power Architecture downloads and documentation: Upgrade your Cell BE SDK components
Download new and improved Cell Broadband Engine (Cell BE) SDK components -- the Full-System Simulator, the Software Sample and Library Source Code, and the XL C Alpha Edition compiler. Try out the latest Watson Sparse Matrix Package with a new symmetric indefinite solver with diagonal pivoting. Plus, read more on z9 109, z/OS, p5, and the IntelliStation POWER 185, and get the 750GX/GL Evaluation Board Schematics. And plan your summer Redbooks residency.
|
|
Articles |
|
24 Mar 2006 |
|
| |
Testing and measuring the TAMS 3011, Part 3: Porting a screen-management utility to eCos
See the process of porting the Berkeley curses library from UNIX to eCos, picking up a few fragments of the Berkeley C library extensions along the way -- and learn about some general issues of porting from UNIX to eCos.
|
|
Articles |
|
24 Mar 2006 |
|
| |
SoC drawer: Detecting and correcting I/O and memory errors
SoCs (systems-on-chips) are often deployed in communications, storage, network processing, and mission-critical embedded data processing systems. A reliable SoC-based system must mitigate and control environmentally induced errors in stored or transported data. It is impossible to fully prevent data loss, but engineering due diligence is required to ensure that systems are as safe as practically possible given current data coding methods for error detection and correction. This article examines methods to minimize potential data corruption and to maximize system safety when uncorrectable errors do occur.
|
|
Articles |
|
21 Mar 2006 |
|
| |
Everything you ever wanted to know about C types, Part 3: Implementation details
The C type system has changed a lot since the 1970s. Part 3 in the "Everything you ever wanted to know about C types" series reviews some of the quirks that particular implementations have had and discusses the changes the C99 language revision introduced.
|
|
Articles |
|
19 Mar 2006 |
|
| |
Migrating from x86 to PowerPC, Part 9: Sensors, sensors, sensors!
From schematics to code, get a leg up on building your own robot submarine.
Building on previous successes, Lewin Edwards shows how to add more sensors to your
submarine, looking at the design requirements of different sensors and ways of
sanity checking the results they provide.
|
|
Articles |
|
14 Mar 2006 |
|
| |
Standards and specs: Not by UNIX alone
Technology professionals have loosely used the term "UNIX" since the first person had to explain the difference between the Berkeley and AT&T flavors, so it's not surprising to find as many UNIX standards as there are versions of the operating system. Peter Seebach wades through the wellspring of UNIX standards and sorts them out for you, concluding that the rumors of the death of UNIX are (as usual) greatly exaggerated.
|
|
Articles |
|
08 Mar 2006 |
|
| |
Multifunction multimedia machine, Part 4: Mixing hardware and software for cost control
Explore the technical issues in video playback, and see how a blend of hardware and software achieves good performance at a reasonable cost. Also, Lewin Edwards reveals that MP3 does not mean MPEG-3, which alone is worth the price of admission.
|
|
Articles |
|
07 Mar 2006 |
|
| |
Testing and measuring the TAMS 3011, Part 2: An introduction to eCos
The eCos embedded operating system offers an alternative to UNIX-style operating systems for development work. This article examines how its architecture influences the development process, building a sample application and exploring the differences in architecture between eCos and UNIX.
|
|
Articles |
|
24 Feb 2006 |
|
| |
SoC drawer: Shared resource management
The goal of a system-on-a-chip (SoC) is to provide a single-chip system, and therefore SoC resource analysis and sizing is critical. Failure to properly size processing, memory, or I/O needed by software services can kill an SoC project. But all too often, SoC design analysis focuses on processing at the expense of memory or I/O sizing. And even when memory and I/O are sized properly, efficient use of these resources by software services can still be tricky. Any mis-sizing or mismanagement of memory and I/O on an SoC can at the least cause significant project delay and rework. This article examines sizing estimation and resource sharing pitfalls that the system architect should know well.
|
|
Articles |
|
21 Feb 2006 |
|
| |
Everything you ever wanted to know about C types, Part 2: Floating point and derived types
The C type system is often misunderstood or overlooked. This article, the second in a series, discusses the derived types, or types that are built from other types, and some of the interactions that occur when data of multiple types are mixed.
|
|
Articles |
|
14 Feb 2006 |
|
| |
Meet the experts: An interview with the compiler
Got questions about optimizing code for the Cell Broadband Engine (Cell BE) processor? Questions like, when to inline? When to insert an ifetch--and when to inline an ifetch (and what IS an ifetch?) And where do no-ops go? These questions and many others will be addressed in this exclusive Q and A session.
|
|
Articles |
|
14 Feb 2006 |
|
| |
An introduction to compiling for the Cell Broadband Engine architecture, Part 1: A bird's-eye view
This five-part tutorial series helps you understand the Cell Broadband Engine (Cell BE) architecture and gives you a basic intuition for programming issues on it, insight into the compiler challenges presented by it, and an understanding of the techniques and solutions proposed by the IBM compiler. In Part 1, meet the Cell BE processor from a compiler-writer's perspective, and get a bird's-eye view of a number of the unique challenges it poses. Part 1 provides useful background information relevant to the other tutorials in the series.
|
|
Tutorials |
|
07 Feb 2006 |
|
| |
An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory
Fifth and last in the "An introduction to compiling for the Cell Broadband Engine architecture" series, this tutorial discusses techniques for managing data in the local store of the Synergistic Processor Elements (SPEs) of a Cell Broadband Engine (Cell BE) processor. Learn particular techniques such as double-buffering and maintaining a reasonably efficient software cache.
|
|
Tutorials |
|
07 Feb 2006 |
|
| |
An introduction to compiling for the Cell Broadband Engine architecture, Part 4: Partitioning large tasks
This tutorial, fourth and penultimate in the "An introduction to compiling for the Cell Broadband Engine architecture" series, discusses ways to partition code to run across the multiple cores available in a Cell Broadband Engine (Cell BE) processor. It gives particular attention to efficient partitioning of code to allow larger programs or data sets to be manipulated using the 256KB of local store available on the Synergistic Processor Elements (SPEs).
|
|
Tutorials |
|
07 Feb 2006 |
|
| |
An introduction to compiling for the Cell Broadband Engine architecture, Part 3: Make the most of SIMD
Third in the "An introduction to compiling for the Cell Broadband Engine architecture" series, this tutorial discusses the compiler issues in optimizing code to run efficiently on SIMD-capable processors. In particular, it shows how to optimize code that must run both on the VMX SIMD engine of the PowerPC core of the Cell Broadband Engine (Cell BE) processor, and also on the SIMD-only Synergistic Processor Elements (SPEs).
|
|
Tutorials |
|
07 Feb 2006 |
|
| |
An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE
Second in the "An introduction to compiling for the Cell Broadband Engine architecture" series, this tutorial discusses specific issues in optimizing code to run effectively on the Synergistic Processor Elements (SPEs) in the Cell Broadband Engine (Cell BE) processor.
|
|
Tutorials |
|
07 Feb 2006 |
|
| |
Power Architecture directions: Power.org at the one-year crossroads
As Power.org celebrates its first birthday, take a look at what happened in year one and what's ahead. MacLaren Harris interviews Marketing Programs Manager for Power.org Jesse Stein and discovers what is working and what needs work; how Power.org has grown and what has been achieved; and how individual developers can participate.
|
|
Articles |
|
27 Jan 2006 |
|
| |
SoC drawer: Real-time resource management
Systems-on-chips (SoCs) can support applications ranging from those that simply need to maximize throughput to those that must meet hard real-time deadlines. This article gives an in-depth look at SoC design for real-time applications. Get a review of best-effort, soft real-time, and hard real-time requirements, along with a detailed examination of how an SoC can best support traditional real-time scheduling policies and resource feasibility testing.
|
|
Articles |
|
17 Jan 2006 |
|
| |
Multifunction multimedia machine, Part 3: Scripting and scaling for fun and profit
Lewin Edwards looks at the history and design of X and why it matters for an embedded graphics system and introduces a basic scripting language for controlling a multimedia display device.
|
|
Articles |
|
10 Jan 2006 |
|
| |
Everything you ever wanted to know about C types, Part 1: What's in a type?
This article, first in a four-part series, introduces the basics of the C type system, with an overview of what it means to talk about type and a discussion of the basic types (integer and floating point) in some detail.
|
|
Articles |
|
03 Jan 2006 |
|
| |
Standards and specs: An unsung hero: The hardworking ELF
The ELF object module format has had wide-ranging effects on software development for multiple platforms. Peter Seebach looks at the history of the ELF specification and why it's been so useful.
|
|
Articles |
|
20 Dec 2005 |
|
| |
SoC drawer: SoC concurrent development
A system-on-a-chip (SoC) can be more complex in terms of hardware-software interfacing than many earlier embedded systems because an SoC often includes multiple processor cores and numerous I/ O interfaces. The process of integrating and testing the firmware-hardware interface can begin early, but without good management and testing, the mutability of firmware and early stages of hardware design simulation can lead to disastrous setbacks for a project. This article teaches system designers about tools and methods to minimize project churn.
|
|
Articles |
|
20 Dec 2005 |
|
| |
A brief introduction to IBM XL compilers
The IBM XL compilers are the result of years of research, and can compile C/C++ and Fortran code on a variety of Power Architecture technology-based systems and operating systems. The broad scope of these compilers illustrates the strength and breadth of Power Architecture technology.
|
|
Articles |
|
15 Dec 2005 |
|
| |
PowerPC system-on-a-chip introduction
System-on-a-chip (SoC) design is becoming an increasingly attractive alternative to system developers -- and the PowerPC 400 series of processors are a perfect match for this philosophy. Read on to find out why.
|
|
Articles |
|
15 Dec 2005 |
|
| |
Embedded operating systems for IBM Power Architecture technology
To Linux or not to Linux? Embedded developers love using Linux because of the wealth of tools and applications available for it; but it doesn't have all the real-time capabilities that some embedded applications need. This article looks at some operating system options for dealing with embedded applications.
|
|
Articles |
|
15 Dec 2005 |
|
| |
The year in Power Architecture technology: The best of 2005
The year that just was (or perhaps is about to just have been) has been chock full of Power Architecture news -- from Apple's departure from the Power Architecture family to the up and coming Cell Broadband Engine (Cell BE) processor; from Blade.org to Power.org; and from being named fastest growing semiconductor supplier of 2005 to being named 2005 Top Fab, find out why Power Architecture technology is having the best year ever.
|
|
Articles |
|
15 Dec 2005 |
|
| |
POWER to the people
In the last decade alone, IBM scientists have announced one semiconductor breakthrough after another: copper technology, silicon-on-insulator, silicon germanium, strained silicon, and low-k dielectrics. All of these technologies came out of IBM's fertile in-house research community. This prowess in modern chipmaking know-how didn't come out of a vacuum -- rather, it came out of the hermetically-sealed clean rooms of the most advanced R & D department in the semiconductor industry.
|
|
Articles |
|
15 Dec 2005 |
|
| |
IBM PowerPC 970FX power-on reset mechanism
The sophisticated PowerPC 970FX processor requires more sophisticated power-on reset logic. Find out what you need to know to develop systems based on this new processor.
|
|
Articles |
|
15 Dec 2005 |
|
| |
Implications of Power Architecture technology and IBM eServer OpenPower for IBM and the industry
What does the OpenPower initiative herald for open systems and the Power Architecture? In this interview, Adalio Sanchez, general manager, IBM eServer pSeries line, talks about how OpenPower aims to bring the dynamics of the open source community to the hardware realm.
|
|
Articles |
|
15 Dec 2005 |
|
| |
Just like being there: Papers from the Fall Processor Forum 2005: Introducing the IBM PowerPC 970MP
This Fall Processor Forum paper explores the PowerPC 970MP, a 90nm-process, dual-core version of the PowerPC 970FX with remarkable, dynamic power-saving features. It's like no 64-bit dual-core PowerPC processor you've ever met before. Read why.
|
|
Articles |
|
14 Dec 2005 |
|
| |
Cell Broadband Engine processor DMA engines, Part 1: The little engines that move data
A single Cell Broadband Engine (Cell BE) processor consists of one PowerPC core and eight SPEs each having their own DMA engine. The DMA engines are a key component of the overall Cell Broadband Engine Architecture (CBEA) as they move data between SPEs and the PowerPC core. Any operating system or application wishing to utilize the SPE depends on the DMA engines to manage work flow on behalf of the SPEs.
|
|
Articles |
|
06 Dec 2005 |
|
| |
Just like being there: Papers from the Fall Processor Forum 2005: Application-customized CPU design
This Fall Processor Forum paper explores the customized IBM PowerPC processor designed for the Microsoft XBox 360, designed and optimized for high-volume production, low cost, and quality -- with an array of testing and debug features to reduce system time-to-market. It boasts three 3.2GHz high-frequency PowerPC processor cores, and it's like no chip you've ever met before. Read why.
|
|
Articles |
|
06 Dec 2005 |
|
| |
Meet the experts: David Krolak on the Cell Broadband Engine EIB bus
Understanding the Element Interconnect Bus (EIB) is an essential component to maximizing performance on the Cell Broadband Engine (Cell BE) Architecture. The lead designer and EIB project manager sit down for an hour with developerWorks' Meet The Experts to discuss ring versus interconnect buses, data arbiters, and bus protocols.
|
|
Articles |
|
06 Dec 2005 |
|
| |
Power Architecture community calendar: IBM wins National Medal of Honor
IBM scores the National Medal of Technology for innovation and continues to innovate by unveiling a new SOI-less, hybrid-orientation process that speeds pFET transistors yet doesn't affect nFET performance. Visit the first Power Architecture design center that is outside IBM control. View year-end online conferences (on SoC and processor design), and plan for such 2006 events as CES, DAC, PartnerWorld, and Embedded Systems.
|
|
Articles |
|
01 Dec 2005 |
|
| |
Cell Broadband Engine Architecture and its first implementation
Explore the first implementation of the Cell Broadband Engine (Cell BE) Architecture, developed jointly by Sony, Toshiba, and IBM, and get an up-close look at its performance figures and characteristics.
|
|
Articles |
|
29 Nov 2005 |
|
| |
Signals as a Linux debugging tool
By focusing on the analysis of data captured using signal handlers, you can speed up the most time-consuming part of debugging: finding the bug. This article gives a background on Linux signals with examples specifically tested on PPC Linux, then goes on to show how to design your handlers to output information that lets you quickly home in on failed portions of code.
|
|
Articles |
|
29 Nov 2005 |
|
| |
Power Architecture downloads and documentation: Cell Broadband Engine resources on alphaWorks
Download Cell Broadband Engine (Cell BE) technology and a graphical LPAR monitor. Update your Blue Gene Task Layout Optimizer and your PowerPC 970 full-system simulator. And discover fascinating articles on Advanced POWER Virtualization, Attached Network Storage, MRAM and spintronics, and how to simulate PowerPC hardware for Linux development.
|
|
Articles |
|
29 Nov 2005 |
|
| |
Just like being there: Papers from the Fall Processor Forum 2005: Unleashing the Cell Broadband Engine Processor
This paper from the MPR Fall Processor Forum 2005 explores the Cell Broadband Engine (Cell BE) Processor's Element Interconnect Bus (EIB). Designed to handle the bandwidth demands of a nine-core processor running at 3GHz, it's like no bus you have ever met before. Read why.
|
|
Articles |
|
29 Nov 2005 |
|
| |
Meet the experts: The Mambo team on the IBM Full-System Simulator for the Cell Broadband Engine processor
The IBM Full-System Simulator for the Cell Broadband Engine (Cell BE) processor, affectionately known inside IBM as Mambo, is a key component of the newly posted offerings on alphaWorks. Meet some of the members of the team that pulled it together, and hear about the simulator in their own words.
|
|
Articles |
|
22 Nov 2005 |
|
| |
Meet the experts: Alex Chow on Cell Broadband Engine programming models
A critical component of programming for the Cell Broadband Engine (Cell BE) processor is understanding the workload in order to choose the right programming model. Alex Chow of IBM recently proposed several programming models ranging in complexity from a small single SPU to a large interconnected multi-SPU program. developerWorks talks with Alex about some of the programming models he proposed.
|
|
Articles |
|
22 Nov 2005 |
|
| |
PowerPC Architecture Book
This three-volume set defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions.
|
|
Articles |
|
16 Nov 2005 |
|
| |
PowerPC Architecture Book, Version 2.02
This 3 volume set, Version 2.02, defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions for the IBM POWER5 processor family. Verson 2.01 describes POWER4 and POWER4+ processors.
|
|
Articles |
|
16 Nov 2005 |
|
| |
PowerPC Architecture Book, Version 2.02
This three-volume set, Version 2.02, defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions for the IBM POWER5 processor family. Verson 2.01 describes POWER4 and POWER4+ processors.
|
|
Articles |
|
16 Nov 2005 |
|
| |
Meet the experts: Dan Brokenshire and Sid Manning on the alphaWorks downloads for the Cell Broadband Engine
Meet the downloads: Sid Manning and Dan Brokenshire of IBM tell what's in 'em and answer tough questions like "Why Linux?" and (more importantly) "Why Linux on Intel?"
|
|
Articles |
|
16 Nov 2005 |
|
| |
Just like being there: Papers from the Fall Processor Forum 2005: Unleashing the power of the Cell Broadband Engine
This paper from the MPR Fall Processor Forum 2005 explores programming models for the Cell Broadband Engine (CBE) Processor, from the simple to the progressively more advanced. With nine cores on a single die, programming for the CBE is like programming for no processor you've ever met before. Read why.
|
|
Articles |
|
16 Nov 2005 |
|
| |
Power Architecture community calendar: Cell Broadband Engine developer environment arrives
Now available, a complete programming environment for the Cell Broadband Engine (CBE) -- a processor environment simulator, XL C and GCC compilers, an OS kernel, toolchain, library, and samples, as well as a CBE resource center. And, IBM and Sun agree to support Solaris on Blades, and Power.org cranks up technology seminars with three new academic partners. Then plan for such Fall events as Semicon Japan, PowerPC technical briefings in China, and assorted webcasts and Redbook workshops.
|
|
Articles |
|
15 Nov 2005 |
|
| |
Power Architecture downloads and documentation: Complete developer environment for the Cell Broadband Engine
Download a complete programming environment for the Cell Broadband Engine (CBE) -- the software development kit, a processor environment simulator, XL C and GCC compilers, an OS kernel, toolchain, library, and samples -- to get you started. Visit the new Cell Broadband resource center, a home for articles, tutorials, forums, and news of the CBE processor. And discover fascinating articles on these technologies, as well as articles on BladeCenter, POWER Virtualization, and System z9.
|
|
Articles |
|
11 Nov 2005 |
|
| |
RAID on Linux on POWER
Learn about software and hardware redundant array of independent disks (RAID) implementations on a Linux on POWER server. In some regards, this paper is a response to some of the questions and pitfalls in RAID setup. Therefore, this paper includes a foundation on RAID itself, the Linux on POWER boot process, software and hardware RAID, and an example of how to configure hardware RAID.
|
|
Articles |
|
03 Nov 2005 |
|
| |
Clustering solutions for Linux on IBM System p5 Express servers
Learn how to build a Linux High Availability (HA) cluster and a High Performance Computing (HPC) cluster on IBM POWER processor-based servers.
|
|
Articles |
|
02 Nov 2005 |
|
| |
Debugging simulated hardware on Linux, Part 1: Device driver debugging
This two-part series is geared toward easing device driver development. This first part illustrates proven methods you can use to test the complete code flow of a device driver during the design, development, and debugging stages.
|
|
Articles |
|
02 Nov 2005 |
|
| |
Power Architecture community calendar: Xbox 360 unveiled
Look inside Microsoft Xbox 360's trio of PowerPC cores; sneak a peek at P.A. Semi's plans for a new low-power processor, the PWRficient; and discover how IBM is "sharpening" its blades for 2006. And plan for Fall events such as the IEEE Silicon Debug and Diagnosis Workshop, the System-on-Chip symposium, and assorted webcasts and Redbook workshops.
|
|
Articles |
|
01 Nov 2005 |
|
| |
Standards and specs: Digital rights management: When a standard isn't
Whether you're a buyer or a seller of a product, the essential goal of standardization is to make interoperability possible, allowing communication with anyone else using the same protocol and media. In some cases though, vendors have specific reasons for not being compatible -- and those vendors have developed a standard for incompatibility, digital rights management (DRM). The goal of DRM is to limit compatibility because things which are compatible can be copied and distributed freely. In this installment, Peter Seebach looks at a potential oxymoron -- standards designed to subvert and prevent interoperability.
|
|
Articles |
|
01 Nov 2005 |
|
| |
SoC drawer: Function allocation and specification
The system-on-a-chip (SoC) has emerged as the ideal replacement for multipart chipsets. The SoC design promises a single-chip solution, lower power, less board real estate, simpler integration, and lower part counts -- all of which are clearly quite attractive for emergent embedded products. However, packing all the resources needed into a single-chip solution is no easy task: mistakes in sizing on-chip resources require spinning the ASIC or giving up on the single-part solution and adding to the pin and part counts. In this article, Sam Siewart reviews approaches for the early function allocation analysis required to architect an SoC.
|
|
Articles |
|
01 Nov 2005 |
|
| |
Power Architecture downloads and documentation: Blue Gene tools and residency
Find a wealth of Blue Gene resources, an updated Post-Link Optimization for Linux on POWER, new and updated documentation on Power Architecture boxen, the latest Redbook Residency opportunities -- and much more.
|
|
Articles |
|
27 Oct 2005 |
|
| |
Testing and measuring the TAMS 3011, Part 1: Embedded Linux cross-development
The TAMS 3011 offers a PowerPC embedded environment with tools and features familiar to embedded developers. This article subjects it to the Zork test.
|
|
Articles |
|
25 Oct 2005 |
|
| |
Standards and specs: Early adopters
Whether a standard will succeed and be widely adopted is ambiguous at first, regardless of who endorses it -- a major player or a fringe element. So why would people put all their eggs in a standards basket when that basket might not exist tomorrow? Join Peter Seebach as he shows the potential advantages of adopting a standard before it becomes one. (Of course, he hasn't forgotten the potential disadvantages, too.)
|
|
Articles |
|
18 Oct 2005 |
|
| |
Power Architecture community calendar: Cell Broadband Engine Processor debuts in new Blade server
Blades get Cell BE Processors and a cut in price to run Linux; POWER5+ debuts with two POWER5s and cache on one module; and small businesses get 22 new, affordable managed-services products. As well as find information on the Fall Processor Forum 2005, IBM Webcasts, and other events worthy of your attention.
|
|
Articles |
|
17 Oct 2005 |
|
| |
PowerPC processor tips: Two PowerPC 750GXs are better than one
Achieve a level of high reliability in a microprocessor system by adding a second identical processor to a system to monitor and verify the system processor operation -- also known as the lockstep processor technique. This tip illuminates the integrated lockstep facility (LSF) in the IBM PowerPC 750GX processor.
|
|
Articles |
|
17 Oct 2005 |
|
| |
Power Architecture downloads and documentation: Subscription service updates
Subscribe to support bulletin updates for Cluster Systems Management and AIX, and get the following dowloads: techniques for performance tuning the eServer JS20 BladeCenter running Linux on PowerPC 970, the PowerPC 405 Evaluation Kit, a utility to power and frequency scale the PowerPC 970, and the IBM Softcopy Reader. Read the R&D Journal double issue on Blue Gene and POWER5 and packaging, how to simplify your storage infrastructure, three books on Blue Gene (on hardware, sysadmin, and application development), how to secure your e-mail server with Linux, and discover the z/OS technical library.
|
|
Articles |
|
12 Oct 2005 |
|
| |
Migrating from x86 to PowerPC, Part 8: Add stepper motors to the vehicle control module
Lewin Edwards reviews the I/O expansion possibilities for the slave microcontroller on the robot submarine. The Inter-IC Communication (I2C) bus provides a simple and compatible way to expand the submarine's I/O options and connect it to a number of stepper motors.
|
|
Articles |
|
11 Oct 2005 |
|
| |
Meet the experts: On open source firmware development
Slimline Open Firmware (SLOF) provides a largely machine-independent BIOS, illustrating what is needed to initialize and boot Linux, a hypervisor, or any other operating system or virtualization layer on PowerPC-based machines based on the de-facto industry Open Firmware boot standard. Join three experts as they discuss the decisions in developing SLOF and where they'd use it and provide a picture of the boot-up process under SLOF.
|
|
Articles |
|
11 Oct 2005 |
|
| |
An embedded view of the Mac mini, Part 5: Working with USB
Peter Seebach gives an overview of writing a userland (non-kernel) driver for a USB device, allowing his photo kiosk to accept cash, and the author to get rich quick, one dollar at a time.
|
|
Articles |
|
04 Oct 2005 |
|
| |
SoC drawer: The resource view
A system-on-a-chip (SoC) can provide a single-chip solution, lower power usage, better performance, more frugal use of board real estate, simpler integration, and lower part counts. Compared to multichip solutions, the SoC has huge advantages, but mistakes in sizing on-chip resources require spinning the ASIC and result in high cost. This article introduces approaches for SoC design from a resource perspective. The SoC design concept has appeal in a broad range of computing applications, from supercomputing to embedded systems.
|
|
Articles |
|
04 Oct 2005 |
|
| |
Power Architecture community calendar: New Cell development support sets
In the news, Toshiba takes Cell developers to the next level! And: spintronics finally gets some logic; peek at the next generation of memory; a gas-powered MP3 player; C4NP solder bump process becomes a reality; and more. Plus, we answer the question: "Who's to blame when nanometer IC designs fail?" As well as events, new webcasts, and Redbook-sponsored workshops all around the globe.
|
|
Articles |
|
30 Sep 2005 |
|
| |
PowerPC processor tips: Improve PowerPC 970FX performance
The IBM PowerPC 970FX processor is a superscalar design with multiple, pipelined execution units. A well-optimized compiler and tuned operating system are important for getting the most performance from the processor -- however, here are six additional things you can do to improve performance.
|
|
Articles |
|
30 Sep 2005 |
|
| |
Power Architecture downloads and documentation: PowerPC 405 and 440 core models for EDA tools
Download PowerPC 405 and 440 core models for Open SystemC-compatible EDA design tools. Plus, get the latest in the ABCs of z/OS Programming series, vector multimedia extension programming, more on the z9/zSeries Connectivity Handbook, a 970FX design guide, IBM Blue Logic ASICs, and Redbooks on z/OS, zSeries, and z9.
|
|
Articles |
|
28 Sep 2005 |
|
| |
Meet the PowerPC 405 Evaluation Kit
Get a brief introduction to the integration methodology for system-on-chip (SoC) designs for low-power consumer applications using embedded processor cores based on Power Architecture technology.
|
|
Articles |
|
27 Sep 2005 |
|
| |
ChipBench System Level Design
Use the ChipBench System Level Design tool to create and simulate a design constructed from SystemC models of IBM PowerPC 4xx processor cores.
|
|
Tutorials |
|
27 Sep 2005 |
|
| |
Power Architecture directions: Future directions and how to get there -- with Power Architecture technology
In this interview, Dr. Bijan Davari talks to McLaren Harris about his vision on how the role of the processor is changing in today's systems.
|
|
Articles |
|
16 Sep 2005 |
|
| |
Build standard and application-specific single-board computers with Power Architecture technology
Power Architecture technology's open nature brings you flexibility in your system design: because compatibility is assured, you can outsource the design of the chips themselves to third parties. In this article, learn how Momentum Computer builds systems based on the PowerPC 750GX for a variety of customers.
|
|
Articles |
|
16 Sep 2005 |
|
| |
Create blades using Power Architecture technology
The IBM BladeCenter JS20 server brings the 64-bit computational ability of the PowerPC 970 processor to the blade server space. Find out how this new offering could change the face of the server market.
|
|
Articles |
|
16 Sep 2005 |
|
| |
An introduction to Power Architecture 64-bit computing: PowerPC 970FX
64-bit computing is well established on the IBM zSeries and POWER-based pSeries systems. Nonetheless, with the introduction of the PowerPC 970 processor family, 64-bit computing is now available on the desktop, on value-priced servers, and to the embedded community. This article gives an overview of 64-bit computing and discusses the advantages of a 64-bit operating system environment.
|
|
Articles |
|
16 Sep 2005 |
|
| |
AMCC and Power Architecture technology
When AMCC needed a processor architecture for its embedded products, it purchased the intellectual property behind the PowerPC 400 series of chips. Find out how these chips fit into AMCC's plans.
|
|
Articles |
|
16 Sep 2005 |
|
| |
Carrier-grade Linux for Power Architecture processors
Power Architecture processors have a reputation for rock-solid reliability. Now MontaVista's carrier-grade Linux distribution is available for Power Architecture chips. The combination brings the strengths of both technologies to the telco world, where continuous uptime is a must.
|
|
Articles |
|
16 Sep 2005 |
|
| |
The Power in Xilinx
Xilinx has combined Power Architecture technology with its own flexible field programmable gate arrays (FPGAs) to help build flexible systems for numerous customers. Find out how open technology speeds time-to-market.
|
|
Articles |
|
16 Sep 2005 |
|
| |
In search of a total system solution
Both the open source Linux platform and the open Power Architecture technology can scale very well from thin clients to servers. This article proposes a Linux and Power Architecture reference platform that provides a standard base you can modify to fit a number of niches.
|
|
Articles |
|
16 Sep 2005 |
|
| |
Introduction to embedded software development for the IBM PowerPC 970FX processor
The IBM PowerPC 970FX processor is great for embedded programming, but it has a few features, such as 64-bit support, that many embedded developers might not know just how to exploit. Read on to get up-to-speed and learn what you need to know.
|
|
Articles |
|
16 Sep 2005 |
|
| |
Power Architecture technology drives development platform
Power Architecture technology offers powerful performance at a low cost, making it the perfect candidate for an embedded development platform. In this article, Viren Shah of Marvell discusses accelerating product development using Discovery LT.
|
|
Articles |
|
15 Sep 2005 |
|
| |
IBM Power Architecture technology in Cadence
Steve Svoboda of Cadence Design Systems talks about how his company enabled the porting of the PowerPC 440 processor design to TSMC, Ltd. manufacturing processes.
|
|
Articles |
|
15 Sep 2005 |
|
| |
Optimizing the development process
The Power Architecture technology-based Wind River General Purpose Platform, VxWorks Edition, is an excellent base for developers looking to build embedded applications. Leo Samson talks about the latest generation of the product.
|
|
Articles |
|
15 Sep 2005 |
|
| |
Power solutions for Power Architecture technology
As chips grow more complex, so do their power needs: simple linear regulators won't cut it for advanced processors like the PowerPC 750 or PowerPC 970. In this article, Jim Herrmann, Eric Josefson, and Sean Barr of Intersil discuss their company's power solutions for the Power Architecture platform.
|
|
Articles |
|
15 Sep 2005 |
|
| |
Power Architecture community calendar: The IBM Infoprint 4100, Cell, and Power Architecture events in China
What do superfast laser printers, open source and Linux, Cell, Hurricane Katrina, and Power Architecture-related events in China all have in common? They're all news in this edition of the Power Architecture community calendar!
|
|
Articles |
|
15 Sep 2005 |
|
| |
Standards and specs: The ATX case and power supply
The ATX standard allows power supplies and cases to be commodity parts, dramatically reducing the cost of computer design. Lessons learned from the success of this standard show why standardizing parts is important. The BTX standard builds on this, and the blade.org standards work should do likewise.
|
|
Articles |
|
13 Sep 2005 |
|
| |
An architect's view of design challenges and directions
What goes into chip design? Will Power Architecture technology-based chips become an industry standard? Chip-making veteran Jim Kahle says his piece.
|
|
Articles |
|
07 Sep 2005 |
|
| |
The IBM PowerPC 970FX processor for embedded applications
The IBM PowerPC 970FX processor has a number of features that recommend it as an embedded platform. Find out how its backwards compatibility, improved power envelope, and other factors can help your embedded system design.
|
|
Articles |
|
07 Sep 2005 |
|
| |
Green Hills Software development tools and the IBM PowerPC 970FX processor
The IBM PowerPC 970FX is an excellent platform for an embedded system. Green Hills Software offers a variety of development tools to help you use this processor to its fullest potential.
|
|
Articles |
|
07 Sep 2005 |
|
| |
Migrating from x86 to PowerPC, Part 7: Basic design of the vehicle control module
Get an overview of some design decisions involved in configuring a secondary
processor to handle maintenance tasks on your robot submarine, and see some of the
setup code allowing the subordinate processor to interact with the main system.
|
|
Articles |
|
06 Sep 2005 |
|
| |
Power Architecture downloads and documentation: Service updates for clustering software
Download service updates for clustering technology as they become available: CSM, GPFS, LoadLeveler, ESSL, HACMP, and HPS. Plus, find a roundup of the ABCs of z/OS Programming volumes, the z9/zSeries Connectivity Handbook, and Redbooks on z/OS Diagnostic Data Collection/Analysis and z/OS 1.6 Security Services.
|
|
Articles |
|
06 Sep 2005 |
|
| |
Five minutes with: Stanley Kwong on the first Power Architecture-related technical briefings
This question and answer session features Stanley Kwong, the person in charge of worldwide technical briefings for IBM. Stan handles developerWorks briefings and is about to orchestrate the first-ever briefing on the Power Architecture-related dW event in the People's Republic of China. Hear him as he talks about the briefing and comments on technology development in one of the world's most rapidly developing economies.
|
|
Articles |
|
02 Sep 2005 |
|
| |
PowerPC processor tips: New & improved 750GX datasheet
See the newly updated 750GX datasheet, including more on reduced-lead packaging and better package drawings. Learn about the required pullup resistors for the Marvell Discovery III PowerPC controller. And discover how to get a tip on the topic of your choice.
|
|
Articles |
|
01 Sep 2005 |
|
| |
Power Architecture community calendar: The new Cell documents are here!
Find newly released documents to help you "develop" a relationship with the Cell architecture, and take a quick look at the Toshiba companion chip; plus, find a puppy of a pocket-sized portable PowerPC Linux server. Power.org meets in Shanghai, find a webcast to help with chip-design cost management and one which highlights the 970FX in speedier configurations, and Redbook-sponsored workshops all around the globe.
|
|
Articles |
|
30 Aug 2005 |
|
| |
Cell Broadband Engine Architecture from 20,000 feet
The Cell Broadband Engine Architecture (CBEA, or, informally, "Cell") defines a new processor structure based upon the 64-bit Power Architecture technology, but with unique features directed toward distributed processing and media-rich applications. The Cell architecture defines a single-chip multiprocessor consisting of one or more Power Processor Elements (PPEs) and multiple high-performance SIMD Synergistic Processor Elements (SPEs). While each SPE is an independent processor running its own application programs, a shared, coherent memory and a rich set of DMA commands provide for seamless and efficient communications between all Cell processing elements. This article provides a concise view inside the Cell's architecture.
|
|
Articles |
|
24 Aug 2005 |
|
| |
Five minutes with: Dan Greenberg on plans for Cell
Power Everywhere systems offerings program director Dan Greenberg talks about where the Cell Broadband Engine Architecture is going, how IBM intends to encourage collaboration with developers in its deployment, and what collaboration services are already available for Cell development. Plus, he introduces five new detailed developer resources -- an overview of the architecture, the instruction set architecture for the SPU, and three language datasheets.
|
|
Articles |
|
24 Aug 2005 |
|
| |
Power Architecture downloads and documentation: Software models of system components to simulate the PowerPC 970
Download a full-system simulation infrastructure and tools for the PowerPC 970 instruction set. Plus find plenty of Power Architecture-related papers.
|
|
Articles |
|
23 Aug 2005 |
|
| |
Big iron lessons, Part 6: The right coprocessor can help with encryption
Encryption is a key aspect of security for any application or system. Furthermore, encryption is algorithmically complex, requiring significant resources for implementation, and most often, significant hardware acceleration. In this sixth and final installment to the Big iron lessons series, you'll get a review of the modern history of crypto and the encoding hardware and software techniques developed for mainframes that can show you the way forward.
|
|
Articles |
|
16 Aug 2005 |
|
| |
Community calendar
In news: 130nm SiGe processes are here; compile embedded apps for all operating systems; plus more news for the Power community. In events: it's all about design: The IEEE Symposium on High Performance Interconnects, Magma Users Summit on IC, and the EuroConference on Circuit Theory and Design -- and don't miss the webcast series on the PowerPC 970.
|
|
Articles |
|
15 Aug 2005 |
|
| |
Community spotlight
Check out seven manufacturers of PowerPC-enabled RTOS offerings -- DENX, Enea, Green Hills, LynuxWorks, MontaVista, QNX, and Wind River -- and get a peek at their products.
|
|
Articles |
|
15 Aug 2005 |
|
| |
Downloads and documentation
Download technology resources from IBM sites, plus find plenty of Power papers to absorb and IBM residencies to fill.
|
|
Articles |
|
15 Aug 2005 |
|
| |
Shrinking slices: Looking at real time for Linux, PowerPC, and Cell
A great philosopher once said, "Time is an illusion, lunchtime doubly so." What about real time? Specifically, what about Linux and real time? Paul McKenney of IBM discusses processors, computer history, time slices, games, physics, and Linux.
|
|
Articles |
|
15 Aug 2005 |
|
| |
Multifunction multimedia machine, Part 2: Add still images to your media player
The Mac mini offers a viable platform for embedded multimedia development. In this article, Lewin Edwards shows how to make efficient, direct use of the framebuffer to display JPEG files and discusses the issues involved in deciding between direct framebuffer access and using the X server as a graphics driver.
|
|
Articles |
|
09 Aug 2005 |
|
| |
Power Architecture Community Newsletter, 01 August 2005: Community calendar
In news: Biggest big iron ever, plus: building Blade.org. IBM expands the Academic Initiative, enters into litho consortium -- and more. In events: The road to multicore starts with the In-Stat Fall Processor Forum 2005, Hot Chips starts (and ends) with PowerPC papers; and Linux, Linux on POWER, and more Power events (including webcasts!)
|
|
Articles |
|
01 Aug 2005 |
|
| |
Power Architecture Community Newsletter, 01 August 2005: Downloads and documentation
Find a bounty of PowerPC 970FX tools, a tool to monitor Linux/AIX performance, a 64-bit programming guide, process models, plus plenty of Power papers to absorb and IBM residencies to fill.
|
|
Articles |
|
01 Aug 2005 |
|
| |
Big iron lessons, Part 5: Introduction to cryptography, from Egypt through Enigma
When is an enigma not an enigma? When it is deciphered. Learn how to make your own paper enigma encoder, then peruse the source code that duplicates its action to understand its simple yet ingenious inner workings -- as well as the basics of good cryptography. Finally, accept the challenge to crack a simple transposition cipher, because all great encryption architects must first master the art of cryptanalysis.
|
|
Articles |
|
26 Jul 2005 |
|
| |
Migrating from x86 to PowerPC, Part 6: Add vision to your robot submarine
In this episode of the ongoing Kuro Box project, learn how to add a USB camera to the machine. This article includes example Linux code to initialize and read from a USB camera through Video4Linux. Also find a brief introduction to edge detection techniques in captured images.
|
|
Articles |
|
21 Jul 2005 |
|
| |
Power Architecture Community Newsletter, 15 July 2005: Community calendar
In news: New dual-core and low-power PowerPC 9xx processors; recent advances in research; PowerPC product watch, and more. In events: System on Chip for Real Time; PowerPC 970 Hardware design webcast; and lots of Linux.
|
|
Articles |
|
15 Jul 2005 |
|
| |
Power Architecture Community Newsletter, 15 July 2005: Quick community quotes from Walter Ng of Chartered
Chartered's Walter Ng provides more perspective on the company's evolution, the Common Platform, Power Architecture technology, and more.
|
|
Articles |
|
15 Jul 2005 |
|
| |
Power Architecture downloads and documentation: Download bootware-building Slimline Open Firmware, an updated PIBS, and more
Find TimeSys customizable solutions, bootware-building SLOF, an updated PIBS, plus plenty of Power papers to absorb and IBM residencies to fill.
|
|
Articles |
|
15 Jul 2005 |
|
| |
Power Architecture Community Newsletter: Editorial calendar: Fall 2005
Deadlines, due dates, and themes for the 2005 Power Architecture Community Newsletter.
|
|
Articles |
|
07 Jul 2005 |
|
| |
Power Architecture Community Newsletter, 1 July 2005: Community calendar
New, super-concentrated format for all the PowerPC news that's fit to print. This issue: Supercomputing, Power.org, Apple, Cell, and more. In events: no-fee Web-based education: WebSeries webcasts and developerWorks tutorials, introducing "Solaris to Linux Migration," and more.
|
|
Articles |
|
01 Jul 2005 |
|
| |
Power Architecture Community Newsletter, 1 July 2005: Chartered and IBM: Building a common platform for manufacturing
Maybe you've read the announcements of the 90- and 65-nanometer platform, but what does it all mean? Chartered's Walter Ng puts it into perspective -- including where Samsung and Infineon fit in (and how Power Architecture fits in).
|
|
Articles |
|
01 Jul 2005 |
|
| |
Power Architecture downloads and documentation: SoC tutorial, PowerPC 4xx cores, and Slimline Open Firmware
Find one tutorial, two downloads, two docs on Cell and on ASICs, a new IBM Microprocessor 750GL datasheet, and a veritable feast of Redbooks and Redbook Residencies.
|
|
Articles |
|
01 Jul 2005 |
|
| |
Meet the experts: Arnd Bergmann on the Cell BE processor
This question and answer article features Arnd Bergmann of IBM: a kernel hacker with the IBM Linux Technology Center, the Linux on Cell Broadband Engine (Cell BE) processor kernel maintainer, and author of the spufs file system.
|
|
Articles |
|
25 Jun 2005 |
|
| |
Spufs: The Cell Synergistic Processing Unit as a virtual file system
Base platform support for Linux on the Cell has been established and is currently on its way into the mainstream Linux kernel tree. Read about the Cell's unique architecture and the SPU file system interface that allows Linux to run on it.
|
|
Articles |
|
25 Jun 2005 |
|
| |
SoC design with CoreConnect: 128-bit PLB explained
CoreConnect is based on three buses: the Device Control Register (DCR), the Processor Local Bus (PLB), and the On-chip Peripheral Bus (OPB). This architecture lets you connect your IP to the bus that's most suited to it. The objective of this tutorial is to describe the steps required to design a PLB4 IP. PLB4 is the latest 128-bit version of PLB, which is the backbone of CoreConnect. Learn how to design a system-on-chip (SoC) using PLB4, the latest 128-bit version of PLB. Upon completion of this tutorial, you will be able to implement, test, and debug 128-bit PLB IPs for 4xx, 7xx, and 9xx PowerPC cores.
|
|
Tutorials |
|
15 Jun 2005 |
|
| |
Power Architecture Community Newsletter, 08 June 2005: Community calendar
In the news: The IBM/Chartered common design platform; game consoles powered by PowerPC; open source Cell; Apple on x86; and a roundup of chip-related headlines. In the calendar: Intro to Linux on POWER workshops, Reconfigurable Systems and Algorithms, MPSoC'05, IBM DAC notebook, free IBM Web broadcasts -- and much more.
|
|
Articles |
|
08 Jun 2005 |
|
| |
Power Architecture Community Newsletter, 08 June 2005: PowerPC processor tips
Check out the new PowerPC in town: The low-power IBM PowerPC 750GL is now available in limited sampling.
|
|
Articles |
|
08 Jun 2005 |
|
| |
Power Architecture downloads and documentation: Download open source Slimline Open Firmware
Find two new downloads, two updated tools, a gathering of technology-related resources, new data on cooling and power management, eight new Redbooks, and much more.
|
|
Articles |
|
08 Jun 2005 |
|
| |
Power Architecture Community Newsletter, 08 June 2005: Synopsys and IBM: A partnership for design -- and designers
Users of Synopsys DesignWare IP Library can now access Design Views for the just-announced PowerPC 405 and 440 fully synthesizable cores. The Power Architecture Community Newsletter caught up with Synopsys' Norm Kelly to talk about the new synthesizable cores, buying versus building design tools, best practices for designing high-quality IP, and much more.
|
|
Articles |
|
08 Jun 2005 |
|
| |
An embedded view of the Mac mini, Part 4: Perfecting the prototype
In this installment of "An embedded view of the Mac mini," Peter Seebach builds upon the original prototype "photo booth" application using Fink to get third-party software help in photo setup and layout.
|
|
Articles |
|
31 May 2005 |
|
| |
Standards and specs: The Small Computer System Interface (SCSI) standard
SCSI has a reputation as one of the oldest and most widely respected standards in computing, but it also has a reputation for poor price and performance and amazing quirkiness. This month's Standards and specs looks at the history of the legendary SCSI specification.
|
|
Articles |
|
24 May 2005 |
|
| |
Big iron lessons, Part 4: Power, cooling, and performance: Find the right balance
The z990 mainframe system uses active cooling with cycle steering to achieve balance. See how you can incorporate similar emergent cooling and adaptive power control methods into your embedded system designs.
|
|
Articles |
|
17 May 2005 |
|
| |
Migrating from x86 to PowerPC, Part 5: Create a Kuro-based Web album
In the fifth article of the Migrating from x86 to PowerPC series, Lewin Edwards shows how to get a photo album running on the Kuro Box. In the process, he covers embedded systems design goals, Web server security, and shows off a few handy tricks for off-loading processing work to the client system.
|
|
Articles |
|
17 May 2005 |
|
| |
Power Architecture Community Newsletter, 16 May 2005: PowerPC processor tips
Keep your knowledge of the Blue Gene and Cell processors up-to-date with two new document categories.
|
|
Articles |
|
16 May 2005 |
|
| |
Power Architecture Community Newsletter, 16 May 2005: Community calendar
In the news, eavesdrop on the beginning of the universe, pick your place on the dual-core software licensing spectrum, and more. In the calendar, Wind River 2005 Worldwide User Conference, Power.org in Barcelona, the 42nd DAC 2005 Design Automation Conference, and much more.
|
|
Articles |
|
16 May 2005 |
|
| |
Power Architecture downloads and documentation: Download a Linux embedded development suite and an on-chip debugger and simulator
Find the demos for TimeSys' Linux embedded development suite and for Lauterbach's on-chip debugger and simulator, a new approach to organizing and implementing the register-renaming mapper for out-of-order POWER4 processors. Also find 12 updated Redbooks, including how to implement partitions for IBM eServer p5 servers, a metascheduler proof of concept using the Tivoli Workload Scheduler, and a virtual partition manager guide.
|
|
Articles |
|
16 May 2005 |
|
| |
Power Architecture Community Newsletter, 16 May 2005: Profiling partner products
This issue's product spotlight: Magma Design Automation, a processor design tool company specializing in EDA software.
|
|
Articles |
|
16 May 2005 |
|
| |
Multifunction multimedia machine, Part 1: Load Linux on the Mac mini
The Mac mini is an ideal low-cost, high-performance PowerPC development platform for numerous applications. Learn how to install and configure Linux on the mini. Future articles will add the software required to make it into a stand-alone multimedia appliance.
|
|
Articles |
|
10 May 2005 |
|
| |
An embedded view of the Mac mini, Part 3: Rapidly prototype an embedded application
In a continuing look at the Mac mini as an embedded development platform, Peter Seebach shows how to rapidly prototype a simple application, looking at the variety of tools and glue available natively in Mac OS X.
|
|
Articles |
|
04 May 2005 |
|
| |
Power Architecture Community Newsletter, 02 May 2005: Community calendar
Stay up-to-date with the latest headlines, upcoming events, Webcasts, and more. In the news, RosettaNet sets standard for Semicon's data exchange, IBM and National Geographic trace humanity's genetic ancestry, where we are going after Moore's Law, and more. In the calendar, FREE OpenPower and JS20 BladeCenter seminars, 64-bit Linux on POWER workshops, the IEEE International Symposium on Circuits and Systems, the E3 Interactive Entertainment Expo, and much more.
|
|
Articles |
|
02 May 2005 |
|
| |
Power Architecture Community Newsletter, 02 May 2005: PowerPC processor tips
Expand your knowledge of the PowerPC 750FL, now ready for limited sampling.
|
|
Articles |
|
02 May 2005 |
|
| |
Power Architecture downloads and documentation: xCAT toolkit for Linux cluster deployment, updated Redbooks, and more
Find the xCAT toolkit for Linux cluster deployment, an updated programming environments manual for 32 and 64-bit processors, and eight updated Redbooks, including a communications controller migration guide and an introduction to the eServer OpenPower 710.
|
|
Articles |
|
02 May 2005 |
|
| |
Power Architecture Community Newsletter, 02 May 2005: Solving the fabrication dilemma: The MOSIS service
Wes Hansford, Deputy Director of MOSIS, talks about the company's history, multiproject wafer runs, and the future of the Moore's Law.
|
|
Articles |
|
02 May 2005 |
|
| |
Standards and specs: The ins and outs of USB
The USB specification may be an example of that hybrid de jure or de facto standard, one that clearly earned wide acceptance through its technical merit. Learn the history of the USB standard and some of its benefits to users and vendors, as well as where it missed the boat.
|
|
Articles |
|
26 Apr 2005 |
|
| |
Big iron lessons, Part 3: Performance monitoring and tuning
For many developers and engineers, performance is often an afterthought. But when a product functions as designed and has proven stability and the right feature mix, success in the marketplace often depends upon performance. Architectural decisions define the ultimate feasible performance of any product. In this article, learn how performance-monitoring technology initially developed for mainframes can help you improve your own code's performance.
|
|
Articles |
|
19 Apr 2005 |
|
| |
Power Architecture Community Newsletter, 15 Apr 2005: Profiling partner products
Keeping it real (time): This spotlight profiles two products: OSE RTOS from Enea and QNX Neutrino RTOS from QNX.
|
|
Articles |
|
15 Apr 2005 |
|
| |
Power Architecture Community Newsletter, 15 Apr 2005: Community calendar
Stay up-to-date with the latest headlines, upcoming events, Webcasts, and more. In the news, storage virtualization on the move, OpenPower servers tuned specially for Linux, and a vision for Power servers. In the calendar, the Portable Power Developers Conference and the Conference on Lead-Free Components.
|
|
Articles |
|
15 Apr 2005 |
|
| |
Power Architecture downloads and documentation: Updates to Power Architecture tools
Find a Linux on Power post-link optimization utility update, details on a retired PowerPC API library, and an update to the PowerPC 750CX/CXe user's manual.
|
|
Articles |
|
15 Apr 2005 |
|
| |
Standards and specs: Naturally occurring standards
What makes a standard viable without the formal blessing of a standards organization? Should you use such informal standards, or ignore them? Learn more about de facto standards in this month's Standards and specs.
|
|
Articles |
|
12 Apr 2005 |
|
| |
An embedded view of the Mac Mini, Part 2: Free software on a cheap computer
NetBSD and Yellow Dog Linux have both begun to support the Mac Mini. Peter Seebach looks at open source operating system options on this new contender in the embedded PowerPC platform space.
|
|
Articles |
|
05 Apr 2005 |
|
| |
MySQL for Linux on POWER, Part 1: Introduction to creating a database
Learn about the availability of MySQL Database Server for Linux(R) running on IBM(R) POWER(TM) and PowerPC(R) processor-based servers (collectively referred to as Linux on POWER). As a brief guide for application developers using MySQL on Linux on POWER, this paper is intended for MySQL developers and database administrators who are familiar with their system environment, networks, media devices, and disk resources. In Part 2 of this article, read about developing applications for MySQL using PHP, C/C++, Java, Perl, and Python.
|
|
Articles |
|
05 Apr 2005 |
|
| |
Migrating from x86 to PowerPC, Part 4: Build a minimal embedded Web interface
This installment shows you how to use small-footprint, highly portable, Free Software tools to Web-enable your unmanned submarine, in anticipation of browsing its onboard photo library from an underground lair in the next episode.
|
|
Articles |
|
05 Apr 2005 |
|
| |
Power Architecture Community Newsletter, 1 Apr 2005: PowerPC processor tips
This tip provides the details on how to use a JTAG debugger to take CPU2 out of reset, thereby allowing it to execute code.
|
|
Articles |
|
01 Apr 2005 |
|
| |
Power Architecture Community Newsletter, 1 Apr 2005: Community calendar
Stay up-to-date with the latest headlines, upcoming events, Webcasts, and more. In this issue, Blue Gene/L, Cell, photonics and Blade news; InStat Spring Processor forum and Moscow's eighth ExpoElectronica conference events are profiled.
|
|
Articles |
|
01 Apr 2005 |
|
| |
Power Architecture downloads and documentation: Performance simulator for Linux on POWER, Cell documentation, and more
Find the IBM performance simulator for Linux on Power, Cell articles posted to the IBM Microelectronics Technical Library, and the latest documentation and residencies.
|
|
Articles |
|
01 Apr 2005 |
|
| |
Unrolling AltiVec, Part 3: Down and dirty loop optimization
This series has looked at how the AltiVec instruction set can improve performance on G4 and G5 PowerPC chips. With the theoretical discussion covered in Parts 1 and 2, Part 3 tries to actually get some code optimized. This installment of the Unrolling AltiVec series looks at some real-world code that processors might spend a serious amount of time running, and shows how to tweak it to get extra performance.
|
|
Articles |
|
01 Apr 2005 |
|
| |
This hardware, that operating system: Series overview
So, you want this hardware to run that operating system. What's next? Join journeyman Jack-of-all-trades Tim Kelly as he documents the process of porting NetBSD to a PowerPC-based platform. This in-depth look at the components involved in interfacing an operating system to hardware is in a quantitative manner, and offers something for all levels of readers.
|
|
Articles |
|
22 Mar 2005 |
|
| |
Unrolling AltiVec, Part 2: Optimize code for SIMD processing
In this second article of a three-part series, Peter Seebach looks closer at AltiVec, the PowerPC SIMD unit. He explains further how you can effectively use AltiVec, discussing the choice between C and assembly, and shows some of the issues you'll face when trying to get the best performance out of an AltiVec processor.
|
|
Articles |
|
16 Mar 2005 |
|
| |
Power Architecture Community Newsletter, 15 Mar 2005: Profiling partner products
This week's product spotlight features the following five products: PowerPC GNU Toolkits, OCDemon Flash Memory Programmer, and OCD Commander by Macraigor Systems; also VxWorks 6.0 and visionICE II by Wind River.
|
|
Articles |
|
15 Mar 2005 |
|
| |
A moment of Xen: Virtualize Linux to test your apps
Xen is a virtualization technology available for the Linux kernel that lets you enclose and test new upgrades as if running them in the existing environment but without the worries of disturbing the original system. The author shows you how to install Xen using Fedora Core, but once installed, everything works the same in Xen on any distribution. Take a look at virtualization on Linux and see the benefits of having a sandbox for testing new software, as well as a playground for running multiple virtual machines on the same Linux box.
|
|
Articles |
|
15 Mar 2005 |
|
| |
An embedded view of the Mac Mini, Part 1: Apple's new PowerPC BSP
The Mac Mini isn't just competition for Shuttle computers and mini-tower PCs. It's also competition for the much smaller embedded development boards that many users are building custom applications around. Peter Seebach takes a look at the Mac Mini as an embedded development platform.
|
|
Articles |
|
15 Mar 2005 |
|
| |
Big iron lessons, Part 2: Reliability and availability: What's the difference?
Historically, system architects have taken two approaches to designing reliable computing systems: building highly reliable, fail-safe systems with low probability of failure, or building mostly reliable systems with quick automated recovery. The RAS (Reliability, Availability, Serviceability) concept for system design integrates concepts of design for reliability and for availability along with methods to quickly service systems that can't be recovered automatically.
|
|
Articles |
|
08 Mar 2005 |
|
| |
Migrating from x86 to PowerPC, Part 3: Kuro Box Linux up close
This installment of "Migrating from x86 to PowerPC" moves from the abstract to the concrete, looking into implementation details of the Kuro Box. Lewin Edwards shows how to get the box configured with development tools and device drivers installed and updated.
|
|
Articles |
|
08 Mar 2005 |
|
| |
Power Architecture Community Newsletter, 1 Mar 2005: Profiling partner products
Introducing the product spotlight: MULTI by Green Hills and TimeStorm LDS by TimeSys.
|
|
Articles |
|
01 Mar 2005 |
|
| |
Unrolling AltiVec, Part 1: Introducing the PowerPC SIMD unit
AltiVec? Velocity Engine? VMX? If you've only been casually following PowerPC development, you might be confused by the various guises of this vector processing SIMD technology. In this first installment of a three-part series, Peter Seebach gives you the basics on what AltiVec is, what it does -- and how it stacks up against its competition.
|
|
Articles |
|
01 Mar 2005 |
|
| |
Power Architecture downloads and documentation: Updates to the Linux on POWER toolkit
Check out 30 updates to the Linux on POWER toolkit, download the PowerPC 970FX and PowerPC 750GX/FX Evaluation Kits, and read up on recent Power Architecture Redbooks.
|
|
Articles |
|
01 Mar 2005 |
|
| |
Power Architecture Community Newsletter, 1 Mar 2005: Community calendar
Stay up-to-date with the latest headlines, upcoming events, Webcasts, and more. In this issue, IBM seeks partners for iSeries, meets partners at PartnerWorld, and partners with Zend on Cloudscape.
|
|
Articles |
|
01 Mar 2005 |
|
| |
Build a GCC-based cross compiler for Linux
Get step-by-step instructions for building a cross-compiler so that you can build and develop applications for an alternative platform. Cross-compilers can be useful in many different situations, such as when you develop applications for embedded platforms.
|
|
Tutorials |
|
22 Feb 2005 |
|
| |
Standards and specs: The PCI bus
The widely adopted PCI standard has defeated a large number of competing standards in the marketplace. This month's Standards and specs looks at how the PCI bus won, what the effects of its dominance have been, and what might happen next.
|
|
Articles |
|
22 Feb 2005 |
|
| |
Power Architecture author FAQ
If you're interested enough in Power Architecture technology to read articles on our content area, then you just might have some knowledge to share with your fellow pros. Find out how you can submit your ideas to developerWorks.
|
|
Articles |
|
18 Feb 2005 |
|
| |
Power Architecture Community Newsletter, 15 Feb 2005: MareNostrum: A new concept in Linux supercomputing
The MareNostrum supercomputer at the Barcelona Supercomputing Center, ranked number four in the world in speed in November 2004, is constructed of such totally off-the-shelf parts as IBM BladeCenter JS20 servers, 64-bit 970FX PowerPC processors, TotalStorage DS4100 storage servers, and Linux 2.6. This is its story.
|
|
Articles |
|
15 Feb 2005 |
|
| |
Power Architecture downloads and documentation: Editors, compilers, debuggers, databases, and more
Find a wealth of Power Architecture resources in this issue of Downloads and docs: editors, compilers, debuggers, databases, clustering tools, documentation, and information on IBM Redbook Residencies.
|
|
Articles |
|
15 Feb 2005 |
|
| |
Meet the experts: Scott Handy
The Chiphopper initiative is an aggressive, new, end-to-end program from IBM that lets you port code to eServer even if you don't own an eServer. It's aimed at helping ISVs to easily test, port, and then support applications across all IBM systems from OpenPower to zSeries. developerWorks talked with Scott Handy, VP, WW Linux business strategy at IBM, about what it is and how it works.
|
|
Articles |
|
15 Feb 2005 |
|
| |
Meet the experts: Scott Handy
The Chiphopper initiative is an aggressive, new, end-to-end program from IBM that lets you port code to eServer even if you don't own an eServer. It's aimed at helping ISVs to easily test, port, and then support applications across all IBM systems from OpenPower to zSeries. developerWorks talked with Scott Handy, VP, WW Linux business strategy at IBM, about what it is and how it works.
|
|
Articles |
|
15 Feb 2005 |
|
| |
Data alignment: Straighten up and fly right
Data alignment is an important issue for all programmers who directly use memory. Data alignment affects how well your software performs, and even if your software runs at all. As this article illustrates, understanding the nature of alignment can also explain some of the "weird" behaviors of some processors.
|
|
Articles |
|
08 Feb 2005 |
|
| |
Migrating from x86 to PowerPC, Part 2: Anatomy of the Linux boot process
This installment of "Migrating from x86 to PowerPC" discusses detailed similarities and differences between booting Linux on an x86-based platform (typically a PC-compatible SBC) and a custom embedded platform based around PowerPC, ARM, and others. It discusses suggested hardware and software designs and highlights the tradeoffs of each. It also describes important design pitfalls and best practices.
|
|
Articles |
|
08 Feb 2005 |
|
| |
Power Architecture Community Newsletter: How to contribute
Thank you for your interest in contributing to the Power Architecture Community Newsletter. This article offers guidelines on how the process works -- from submission to publication.
|
|
Articles |
|
07 Feb 2005 |
|
| |
Power Architecture downloads and documentation: XL Fortran, the IBM PowerPC 750GX/FX Evaluation Kit, and more
Check out the XL Fortran 60-day Open Beta, and download the IBM PowerPC 750GX/FX Evaluation Kit, including board and software technical specifications, evaluation board schematics, and an application note that describes step-by-step instructions on how to obtain and build GNU software development tools for use with the evaluation kit software
|
|
Articles |
|
01 Feb 2005 |
|
| |
Big iron lessons, Part 1: FPU architecture, now and then
Floating point provides a convenient, approximate representation of real numbers that can greatly simplify scientific and engineering algorithms. This article gives an overview of two floating point formats used in the z990 architecture and discusses key FPU issues that system architects should consider in new designs. It is intended to assist system architects who are considering FPU integration and want to learn from the rich history of IBM mainframe FPU architecture evolution.
|
|
Articles |
|
01 Feb 2005 |
|
| |
Standards and specs: A house divided
What happens when two coalitions within a standards committee come into conflict, and the dispute doesn't get resolved quickly? The ultrawideband technology standardization issue shows you.
|
|
Articles |
|
25 Jan 2005 |
|
| |
Emulation and cross-development for PowerPC
This article introduces PowerPC emulation and cross-compiling for developers without access to real hardware. It is intended for developers familiar with computer architecture who own an x86-based workstation but are interested in experimenting with PowerPC.
|
|
Articles |
|
18 Jan 2005 |
|
| |
Power Architecture Community Newsletter, 14 Jan 2005: Community calendar
Stay up-to-date with breaking news, upcoming events, and webcasts.
|
|
Articles |
|
14 Jan 2005 |
|
| |
Power Architecture downloads and documentation: Power Architecture tools to help your business
Download these tools to get a closer look at what Power Architecture technology can do for your business.
|
|
Articles |
|
14 Jan 2005 |
|
| |
Meet the experts: Regina Darmoni
This question and answer article features the IBM Program Director of PowerPC licensing, Regina Darmoni. Regina has led the PowerPC licensing effort from the concept stage to the present and talks about general license terms and what's available -- and what it's like to be the little guy.
|
|
Articles |
|
12 Jan 2005 |
|
| |
Meet the experts: Regina Darmoni
This question and answer article features the IBM Program Director of PowerPC licensing, Regina Darmoni. Regina has led the PowerPC licensing effort from the concept stage to the present and talks about general license terms and what's available -- and what it's like to be the little guy.
|
|
Articles |
|
11 Jan 2005 |
|
| |
|
|
Articles |
|
11 Jan 2005 |
|
| |
This is a test article. Please ignore.
This is a test article. Please ignore.
|
|
Articles |
|
11 Jan 2005 |
|
| |
Migrating from x86 to PowerPC, Part 1: Robots and networked appliances on a shoestring
This series on embedded development shows you how to migrate a project prototype from x86 to PowerPC. This initial installment explains the realities and rationale of the project: it introduces the robotic submarines that were the start of the project (and where they came from), and describes the Linux/GCC development environment and the bare-bones Kuro Box PowerPC development board.
|
|
Articles |
|
04 Jan 2005 |
|
| |
From the stacks: Programming the cache on the PowerPC 750GX/FX
Many programs can obtain acceptable performance by simply letting the processor manage its own caching -- however, programs with special requirements (for instance, bootware) may obtain dramatically improved performance by manipulating the cache directly. This excerpt from an IBM Microelectronics Technical Library Application Note discusses cache basics for the PowerPC 750GX and 750FX.
|
|
Articles |
|
04 Jan 2005 |
|
| |
Great moments in microprocessor history
The evolution of the modern microprocessor is one of many surprising twists and turns. Who invented the first micro? Who had the first 32-bit single-chip design? You might be surprised at the answers. This article shows the defining decisions that brought the contemporary microprocessor to its present-day configuration.
|
|
Articles |
|
22 Dec 2004 |
|
| |
The year in Power Architecture technology: The year in microprocessors
From spintronics to clockless CPUs, 2004 was a year of process and research in the microprocessor industry. This article offers a month-by-month look at the highlights of the 2004 microprocessor timeline.
|
|
Articles |
|
22 Dec 2004 |
|
| |
The advantages of using IBM Power Architecture processors in the set-top box
As digital television has become a fact of life the set-top box has reached more and more homes. The IBM PowerPC 4xx processors are a perfect fit for such devices.
|
|
Articles |
|
15 Dec 2004 |
|
| |
Standards and specs, Special Edition: Introducing Power.org
Major electronics companies have come together to form a new standards body focused on Power Architecture technology. This organization will create and promote a family of standards, reference designs, and more. This month's Standards and specs looks at how the new standards body will work, and what it will do.
|
|
Articles |
|
15 Dec 2004 |
|
| |
PowerPC development from the bargain basement
The Kuro Box promises something fairly interesting: a usable single-board PowerPC computer, for only US$160 -- when other PowerPC development boards often cost ten times as much. Peter Seebach guides you through setup and install in this developerWorks hardware howto.
|
|
Articles |
|
14 Dec 2004 |
|
| |
About: Power.org
This interview focuses on the structure and aims of Power.org, a major new standards consortium in the marketplace. Discover what this new body has to do with open standards, customizable processors, consumer devices -- and doughnuts.
|
|
Articles |
|
02 Dec 2004 |
|
| |
Meet the experts: John McCalpin
This question and answer article features IBM Senior Technical Staff Member John McCalpin on his work on the POWER5 and in high performance computing; on the Hypervisor and the size of POWER5 chips; on 128-bit computing -- and even on why he became a computer scientist instead of an entomologist.
|
|
Articles |
|
23 Nov 2004 |
|
| |
Standards and specs: The nitty-gritty on the C committee
The C standard is a few hundred pages full of specifications and requirements. This month's Standards and specs looks at some of the different components of the C standard, and how they might affect Power Architecture developers and implementors.
|
|
Articles |
|
23 Nov 2004 |
|
| |
Save your code from meltdown using PowerPC atomic instructions
Something as simple as incrementing an integer can fail in a concurrent environment. This article illustrates the failure scenario and introduces the PowerPC's coping mechanism: atomic instructions. Learn how to use these assembly-level instructions to update memory correctly, even in the face of concurrency.
|
|
Articles |
|
02 Nov 2004 |
|
| |
From the stacks: TCP/IP checksum vectorization using AltiVec, Part 2
This article, the second in a two-part series, focuses on unrolling loops in ways that allow the AltiVec unit to execute code more efficiently and give the GCC compiler hints for automatically generating vectorized code from plain C.
|
|
Articles |
|
02 Nov 2004 |
|
| |
From the stacks: TCP/IP checksum vectorization using AltiVec, Part 1
This two-part article demonstrates the kinds of performance gains AltiVec can produce on the TCP/IP checksum, or on code similar to it. It gives special attention both to instructions that help improve performance, and to general unrolling and scheduling techniques. The net result? Performance increased by a factor of four.
|
|
Articles |
|
26 Oct 2004 |
|
| |
