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SoC drawer: SoC concurrent development
A system-on-a-chip (SoC) can be more complex in terms of hardware-software interfacing than many earlier embedded systems because an SoC often includes multiple processor cores and numerous I/ O interfaces. The process of integrating and testing the firmware-hardware interface can begin early, but without good management and testing, the mutability of firmware and early stages of hardware design simulation can lead to disastrous setbacks for a project. This article teaches system designers about tools and methods to minimize project churn. 		Articles 20 Dec 2005  
 
SoC drawer: Function allocation and specification
The system-on-a-chip (SoC) has emerged as the ideal replacement for multipart chipsets. The SoC design promises a single-chip solution, lower power, less board real estate, simpler integration, and lower part counts -- all of which are clearly quite attractive for emergent embedded products. However, packing all the resources needed into a single-chip solution is no easy task: mistakes in sizing on-chip resources require spinning the ASIC or giving up on the single-part solution and adding to the pin and part counts. In this article, Sam Siewart reviews approaches for the early function allocation analysis required to architect an SoC. 		Articles 01 Nov 2005  
 
SoC drawer: SoC prognostication
Since its emergence about a decade ago, the SoC (system-on-a-chip) architecture has become the underlying architecture for many embedded systems and scalable supercomputers and is starting to find its way into general purpose computing as well. The SoC embodies what many believe to be the ultimate level of integration: an entire system on one chip. Moore's law and higher levels of integration made the SoC inevitable, but can this continue? And what's next? This article takes a step back to gain perspective on the SoC and to see where it is going in the future. Perhaps the more important question is: where should the highest level of integration be, and what will it enable 25 years from today? 		Articles 05 May 2006  
 
SoC drawer: Detecting and correcting I/O and memory errors
SoCs (systems-on-chips) are often deployed in communications, storage, network processing, and mission-critical embedded data processing systems. A reliable SoC-based system must mitigate and control environmentally induced errors in stored or transported data. It is impossible to fully prevent data loss, but engineering due diligence is required to ensure that systems are as safe as practically possible given current data coding methods for error detection and correction. This article examines methods to minimize potential data corruption and to maximize system safety when uncorrectable errors do occur. 		Articles 21 Mar 2006  
 
SoC drawer: SoCs and the digital content revolution
SoC (system-on-a-chip) architectures could significantly accelerate digital video processing and enable the digital video revolution. Sam Siewert offers an overview of digital video processing and emergent applications in the video realm and shows how SoCs can uniquely accelerate processing. If you're an SoC architect, developer, Power Architecture platform software developer, or anyone creating digital video applications and services, this article is for you. 		Articles 17 Jan 2007  
 
SoC drawer: Eyes inside the silicon
Author Sam Siewert describes basic methods and tools that can provide eyes into the silicon for architects, designers, and engineers working with reconfigurable systems-on-chips (SoCs). SoCs like the Xilinx Virtex line provide a hybrid platform for hardware and software co-design and implementation of real-time services and digital signal processing. Hybrid SoCs employing Power Architecture technology-based software interfacing to highly customized hardware state machines can help designers unlock the power of application-specific hardware acceleration. The integration of the Power Architecture cores with reconfigurable logic provides a powerful prototyping and product platform for SoCs. This power can be better unleashed using trace, debug, and analysis tools to visualize and tune hardware and software interfaces and interaction. 		Articles 10 Oct 2006  
 
SoC drawer: SoC design for hardware acceleration, Part 2
In the SoC design for hardware acceleration series, author Sam Siewert migrates a simple C function to a SystemC specification that can be simulated and verified for ultimate implementation as a hardware function. Part 1 provided the C code and a general overview of video capture, streaming, and processing. Part 2 shows how hardware acceleration of emergent applications, such as video streaming, can benefit from system-on-chip (SoC) design and reconfigurable SoCs with hybrid C software and field-programmable gate array (FPGA)-based functionality. 		Articles 22 Aug 2006  
 
SoC drawer: The resource view
A system-on-a-chip (SoC) can provide a single-chip solution, lower power usage, better performance, more frugal use of board real estate, simpler integration, and lower part counts. Compared to multichip solutions, the SoC has huge advantages, but mistakes in sizing on-chip resources require spinning the ASIC and result in high cost. This article introduces approaches for SoC design from a resource perspective. The SoC design concept has appeal in a broad range of computing applications, from supercomputing to embedded systems. 		Articles 04 Oct 2005  
 
SoC drawer: The Cell Broadband Engine chip: High-speed offload for the masses
Cell Broadband Engine (Cell/B.E.) chips are leading the broadband revolution in computing and provide the core silicon DNA for supercomputing, medical image processing, and many emergent applications, as worldwide connectivity and bandwidth continue to change the world we live in. This article explores the performance of application code on the Sony PLAYSTATION 3's Cell Broadband Engine system running Yellow Dog Linux. A simple program demonstrates how multithreaded applications that use the Synergistic Processing Elements to offload work can enjoy tremendous speedup. 		Articles 17 Apr 2007  
 
SoC drawer: SoC design for hardware acceleration, Part 1
System-on-chip (SoC) designs offer the opportunity to migrate functionality initially implemented in software and firmware into hardware acceleration engines and state machines. Reconfigurable SoCs based on processors in FPGA fabric, such as the PowerPC 405 in the Xilinx Virtex-4, provide a platform for rapid migration of functionality from PowerPC software and firmware to the FPGA logic. Configurable application-specific integrated circuit (ASIC) SoCs can be optimized similarly over product revisions as SoC ASIC roadmap configurations are defined. This article examines methods for software design, specification, and implementation that will simplify future efforts to offload software functionality to hardware. Basic video and image processing algorithms provide working example algorithms for this article and the next. 		Articles 06 Jun 2006  
 
SoC drawer: Shared resource management
The goal of a system-on-a-chip (SoC) is to provide a single-chip system, and therefore SoC resource analysis and sizing is critical. Failure to properly size processing, memory, or I/O needed by software services can kill an SoC project. But all too often, SoC design analysis focuses on processing at the expense of memory or I/O sizing. And even when memory and I/O are sized properly, efficient use of these resources by software services can still be tricky. Any mis-sizing or mismanagement of memory and I/O on an SoC can at the least cause significant project delay and rework. This article examines sizing estimation and resource sharing pitfalls that the system architect should know well. 		Articles 21 Feb 2006  
 
SoC drawer: Real-time resource management
Systems-on-chips (SoCs) can support applications ranging from those that simply need to maximize throughput to those that must meet hard real-time deadlines. This article gives an in-depth look at SoC design for real-time applications. Get a review of best-effort, soft real-time, and hard real-time requirements, along with a detailed examination of how an SoC can best support traditional real-time scheduling policies and resource feasibility testing. 		Articles 17 Jan 2006  
 
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