 |
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IBM BladeCenter QS21 hardware performance glossary
Although there is extensive published data about the hardware performance
features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a
multitude of applications ported to it), there is little on the specific hardware
performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two
Cell/B.E processors as well as an elaborate IO subsystem. This glossary goes with
the article "Evaluating IBM BladeCenter QS21 hardware performance."
In that article, the
authors close the performance gap by providing information about basic latencies, throughputs,
and relative execution times for some key computational benchmark kernels, such as
Linpack and SPEC2000. The article also delivers a basic architectural overview of
the system. And, you can get tips on how to optimize application
performance. |
|
Articles |
|
06 May 2008 |
|
| |
Evaluating IBM BladeCenter QS21 hardware performance
Although there is extensive published data about the hardware performance
features of a single Cell Broadband Engine(TM) (Cell/B.E.) processor (and about the performance of a
multitude of applications ported to it), there is little on the specific hardware
performance features of the IBM BladeCenter(R) QS21 using a coherent SMP node of two
Cell/B.E processors as well as an elaborate IO subsystem. In this article, the
authors close that gap by providing information about basic latencies, throughputs,
and relative execution times for some key computational benchmark kernels, such as
Linpack and SPEC2000. The article also delivers a basic architectural overview of
the system. And, you can get tips on how to optimize application
performance. |
|
Articles |
|
06 May 2008 |
|
| |
Fun with ALF, Part 3: Finding minimum and maximum values
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task context to keep the partial computing
results for each task instance and then combine them. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content. |
|
Articles |
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29 Apr 2008 |
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| |
The little broadband engine that could: DaCS--flexible and complex
In an earlier article in this series, the author introduced a fractal-generation
program built around the IDL interface that showcased the strength of IDL's
straightforward API. Executing the program was almost like calling a function and
getting results. In this article (and using the same basic program), the author
demonstrates the Data Communication and Synchronization library's (DaCS) greater
flexibility and the tradeoff: additional complexity. With DaCS, it's possible to pass the fractal pattern in as an initial argument,
then use buffers to pass data back and forth as they are processed. While this requires
more design work, but it might actually be more efficient. This article also shows that DaCS allows
for much more carefully tuned inputs and outputs. |
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Articles |
|
22 Apr 2008 |
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| |
Cell/B.E. SDK 3.0 tools, Part 1: Using performance tools
This introductory tutorial, designed as a companion for the IBM SDK for
Multicore Acceleration, Version 3.0 (otherwise known as the Cell Broadband
Engine(R) SDK), teaches you how to use five performance tools that reside in the SDK
3.0: OProfile, Cell Performance Counter, Performance Debugging Tool, the PDT Trace
Reader, and FDPR-Pro. The Visual Performance Analyzer, available separately, is also highlighted. |
|
Tutorial |
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15 Apr 2008 |
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| |
Core partners, Part 3: Transforming Gedae-built portable apps
This concise study examines the portability of
applications developed in Gedae by analyzing the work required to move an example
application from a simulation on a PC to actually running on a DSP board (the
Mercury Computer System AdapDev system) to running on a multicore Cell Broadband
Engine(TM) (Cell/B.E.). The article illustrates how architecture considerations were taken into account
when porting the application to each system. You can see the amount of work required to
port the application and the performance of the application on each system. |
|
Articles |
|
08 Apr 2008 |
|
| |
Fun with ALF, Part 2: Converting I/O data
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) task context buffer as a large lookup table to
convert the 16-bit input data to 8-bit output data. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content. |
|
Articles |
|
25 Mar 2008 |
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| |
Fun with ALF, Part 1: Adding large matrices together
In this Cell Broadband Engine(TM) (Cell/B.E.) series, learn how to use the
Accelerated Library Framework (ALF) in the IBM SDK for Multicore Acceleration 3.0 to
add two large matrices together. There is one example for host data
partitioning and one for accelerator data partitioning. The "ALF for Cell/B.E.
Programmer's Guide and API Reference, Version 3.0" (see Resources) is the source for the content. |
|
Articles |
|
18 Mar 2008 |
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| |
The little broadband engine that could: IDL is dead--long live DaCS!
In SDK 3.0, the Data Communication and Synchronization library (DaCS)
provides a sparkling substitute for IDL. DaCS is a set of services to aid the development
of applications and application frameworks in a heterogeneous multi-tiered system.
This article takes you on a tour of the DaCS process model and
explores general DaCS principles, including communication and memory access. |
|
Articles |
|
04 Mar 2008 |
|
| |
The little broadband engine that could: Reviewing the newest little SDK that installs natively on PS3
Come along on a little train tour of the SDK for Multicore Acceleration 3.0
to see what's different for developers and how you can make good use of the SDK,
including native installation on PS3, support for FC7 and RHEL 5.1, enhanced compilers,
Fortran and Ada support, BLAS, ALF, and DaCS--oh my! |
|
Articles |
|
19 Feb 2008 |
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| |
Core partners, Part 2: Using DDT to clean up Cell/B.E. app bugs
Allinea Software's Distributed Debugging Tool (DDT)
provides an easy-to-use, capable debugger that is able to debug complete Cell
Broadband Engine applications, including multiple threads within a single Cell/B.E.
processor and clusters of Cell/B.E. processors. |
|
Articles |
|
05 Feb 2008 |
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| |
Cell/B.E. container virtualization, Part 2: Implementation issues
This three-part series illustrates a
hardware-resource-focused form of software virtualization known as container
virtualization (or operating system virtualization), demonstrated through the open
source project OpenVZ. The series provides a comprehensive overview of all the
components and techniques needed to virtualize the Cell/B.E. processor with software
methods. This second article of the series details the implementation of
dedicated virtualization and partitioning that was described in Part 1 of the series. |
|
Articles |
|
08 Jan 2008 |
|
| |
Cell/B.E. container virtualization, Part 1: Concepts, architectures, and tools
This three-part series illustrates a
hardware-resource-focused form of software virtualization known as container
virtualization (or operating system virtualization), demonstrated through the open
source project OpenVZ. The series provides a comprehensive overview of all the
components and techniques needed to virtualize the Cell/B.E. processor with software
methods. This first article of the series discusses the basic concepts
involved, illustrates the salient points of the OpenVZ and Cell/B.E. architectures
and how they work together, and describes some of the OpenVZ tools. |
|
Articles |
|
11 Dec 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 6: Use simulator consoles, use the ALF wizard, and set IDE preferences
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences. |
|
Tutorial |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 5: Debug and complete dynamic or static performance
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences. |
|
Tutorial |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 4: Configure the application launcher
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences. |
|
Tutorial |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 3: Create the Cell/B.E. simulator environment
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences. |
|
Tutorial |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 2: Create a PPU project
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences. |
|
Tutorial |
|
13 Nov 2007 |
|
| |
Cell/B.E. SDK 3.0, Part 1: Create an SPU project
This introductory tutorial, designed for the IBM SDK for Multicore
Acceleration, Version 3.0 (otherwise known as the Cell Broadband Engine SDK),
explores the Cell/B.E. processor IDE and gives developers a click-for-click
walk-through of building a simple project in this environment. This tutorial is broken into six quick-perform parts dealing with creating an SPU
project, creating a PPU project, creating the Cell/B.E. simulator, configuring the application
launcher, debugging and doing performance analysis, using simulator consoles,
using the ALF wizard, and setting IDE preferences. |
|
Tutorial |
|
13 Nov 2007 |
|
| |
Porting workshop, Part 7: Getting the most performance
The seven quick-read parts of this "Porting workshop" series take
you on a real-world trip from strategy and planning through workload execution,
performance tweaking, optimization, and a solid conclusion. The series describes how to
most effectively port compute-intensive applications to the Cell Broadband Engine
platform. In part seven, the authors evaluate the performance data to date. |
|
Articles |
|
06 Nov 2007 |
|
| |
Cell/B.E.
SDK: Understanding the terminology
A quick-reference glossary of terms you might encounter when installing and
using the Cell Broadband Engine (Cell/B.E.) processor
SDK. |
|
Articles |
|
19 Oct 2007 |
|
| |
Minimize recoding impact, Part 2: Removing obstacles to speedy performance
The first article in the series describes how to do a basic port to the Cell Broadband Engine process. This
second article goes further in hammering out the details, including removing limitations
based on DMA-transfer size, partitioning the program across multiple SPEs, and
improving the program's speed even more. |
|
Articles |
|
16 Oct 2007 |
|
| |
PS3 fab-to-lab, Part 2: Generating and analyzing signals
How do you take the Cell Broadband Engine (Cell/B.E.) processor from an
off-the-shelf Sony PLAYSTATION 3 (PS3) and use it to construct a piece of
Linux(R)-based laboratory equipment (in essence, take the Cell/B.E. from fab to hab
to lab)? In this series, Lewin Edwards shows you how to go from game console to
simple audio-bandwidth spectrum analyzer and function generator. In this article,
the author shows you how to build on the infrastructure from Part 1 to make the
system into a fully operational, if primitive, spectrum analyzer. |
|
Articles |
|
02 Oct 2007 |
|
| |
IBM Installation Toolkit: Loading Linux on POWER
The IBM Installation Toolkit for Linux on POWER simplifies the installation of Linux on
virtualized and non-virtualized Power machines, gives you a bootable rescue DVD, and
provides the software needed to fully exploit the Power platform. Learn to use the
toolkit to install Red Hat Enterprise Linux and SUSE Linux Enterprise Server on
IBM System p and System
i5 machines. |
|
Articles |
|
26 Sep 2007 |
|
| |
The little broadband engine that could: Use multiple SPEs for a single task
Peter Seebach uses a simple, iterative-function fractal generator program to describe how to use multiple
Synergistic Processor Engines (SPEs) to vectorize a single task using the job queue model. |
|
Articles |
|
18 Sep 2007 |
|
| |
Minimize recoding impact, Part 1: How to make an SPE and existing code work together
Traditional porting requires identifying and abstracting out the
architecture-dependent code: making code endian-independent, working through minor
API differences, and including the appropriate header files and libraries. While
this procedure works for getting code to run on the Cell Broadband Engine
(Cell/B.E.) processor, to actually use the extra processing elements, you have to
put in extra work, including reworking the code and rethinking the build process. In
this series, learn to take advantage of the Synergistic
Processor Elements (SPEs) in existing code and only make a minimal impact to the existing code and build process. |
|
Articles |
|
04 Sep 2007 |
|
| |
Porting workshop, Part 3: Initial performance results
The seven, quick-read parts of this series, "Porting workshop," take you on a real-world trip from strategy and planning through workload execution through performance tweaking through optimization to a solid conclusion -- how to most effectively port compute-intensive applications to the Cell Broadband Engine platform. In part three, the authors run and review performance tests and data on the modified code. |
|
Articles |
|
04 Sep 2007 |
|
| |
Porting workshop, Part 2: Original code analysis
The seven, quick-read parts of this series, "Porting workshop," take you on a real-world trip from strategy and planning through workload execution through performance tweaking through optimization to a solid conclusion -- how to most effectively port compute-intensive applications to the Cell Broadband Engine platform. In part two, explore the original code with Linux profiling tools. |
|
Articles |
|
07 Aug 2007 |
|
| |
Porting workshop 1: Processor porting strategies
The seven, quick-read parts of this series, "Porting workshop," take you on
a real-world trip from strategy and planning through workload execution through
performance tweaking through optimization to a solid conclusion -- how to most
effectively port compute-intensive applications to the Cell Broadband Engine
platform. In part one, discover the top three strategies for porting. |
|
Articles |
|
07 Aug 2007 |
|
| |
The little broadband engine that could: Why is my scalar code so slow?
The SIMD-only architecture of the Cell Broadband Engine (Cell/B.E.)
processor's Synergistic Processor Engine (SPE) is an architecture that has no scalar
operations -- all operations are performed on 16-byte vectors. Design code that helps
the Cell/B.E. compiler make efficient use of this architecture. |
|
Articles |
|
07 Aug 2007 |
|
| |
Changes in libspe: How libspe2 affects Cell Broadband Engine programming
The standard library that Power Processor Element (PPE) programs use to
access and manage Synergistic Processor Elements (SPEs), called
libspe, has undergone a major revision. The Cell Broadband Engine (Cell/B.E.)
SDK 2.1 officially changes the library interface from libspe1 to libspe2. In
this article, Jonathan Bartlett introduces the libspe2 concepts and shows how to do basic SPE process management and communication with libspe2. |
|
Articles |
|
17 Jul 2007 |
|
| |
The little broadband engine that could: Mailboxes and interrupts
Meet two more means of communication between the SPE and the PPE -- mailboxes
and signal notification. Mailboxes are special-purpose registers, similar to the I/O
registers used to communicate with peripheral devices on some systems, available on the SPEs and the PPE. Signal notification registers are registers which can be read or written to by the PPE, but which the SPE can only read. |
|
Articles |
|
03 Jul 2007 |
|
| |
Porting practices: Compute-intensive applications
The Cell Broadband
Engine (Cell/B.E.) processor has powerful computation capabilities, but to fully
unleash its power, you need to provide a unique programming paradigm. In this article,
learn best practices for porting a JPEG compression application to the Cell/B.E.
Synergistic Processor Engine (SPE), and see how to take advantage of the processor's unique architecture and avoid its shortcomings. |
|
Articles |
|
19 Jun 2007 |
|
| |
Tech tips: Ten helpful tips when building SPE applications in C
These ten tips can save you
a lot of trouble when you're coding your C applications for the Cell Broadband
Engine (Cell/B.E.) SPU. |
|
Articles |
|
05 Jun 2007 |
|
| |
The little broadband engine that could: An introduction to using SPEs for Cell Broadband Engine development
In this first article in a series on Cell Broadband Engine (Cell/B.E.) development, Peter
Seebach introduces the API used to run programs on SPEs, focusing specifically on
loading code on an SPE and sending data to it for processing. |
|
Articles |
|
05 Jun 2007 |
|
| |
PS3 fab-to-lab, Part 1: Build Linux lab equipment from a Sony PLAYSTATION 3
How do you take the Cell Broadband Engine (Cell/B.E.) processor from an
off-the-shelf Sony PLAYSTATION 3 (PS3) and use it to construct a piece of
Linux-based laboratory equipment (in essence, taking the Cell/B.E. from fab to hab
to lab)? In this series, Lewin Edwards shows you how to go from game console to
simple audio-bandwidth spectrum analyzer and function generator. First up, uncover
the design intent of the project and then make a close inspection of the details of
the user interface implementation as you start a journey to generate and analyze
signals on the Cell/B.E. processor. |
|
Articles |
|
15 May 2007 |
|
| |
Core partners, Part 1: Build high-performance apps for multicore processors
The RapidMind Development Platform provides a simple single-source mechanism to develop portable high-performance applications for multicore processors. In particular, you can use it to develop applications that fully exploit the power of the Cell Broadband Engine (Cell/B.E.) processor's unique architecture by writing only one, single-threaded C++ program using an existing C++ compiler. In this article, author Michael McCool takes you on a guided tour of the RapidMind Development Platform. |
|
Articles |
|
01 May 2007 |
|
| |
Tech tips: SPU vector intrinsics at your fingertips
Know these common C/C++ language extensions intrinsics and greatly simplify the arduous task of using the SPU's assembly language. |
|
Articles |
|
01 May 2007 |
|
| |
SoC drawer: The Cell Broadband Engine chip: High-speed offload for the masses
Cell Broadband Engine (Cell/B.E.) chips are leading the broadband revolution in computing and provide the core silicon DNA for supercomputing, medical image processing, and many emergent applications, as worldwide connectivity and bandwidth continue to change the world we live in. This article explores the performance of application code on the Sony PLAYSTATION 3's Cell Broadband Engine system running Yellow Dog Linux. A simple program demonstrates how multithreaded applications that use the Synergistic Processing Elements to offload work can enjoy tremendous speedup.
|
|
Articles |
|
17 Apr 2007 |
|
| |
Cell/B.E. SDK 2.1: Setting up Fedora Core 6
Before you can install and use the Cell Broadband Engine (Cell/B.E.) processor SDK Version 2.1, you need to get Fedora Core 6 up and running. Here's how. |
|
Articles |
|
17 Apr 2007 |
|
| |
Massively multiplayer online games, Part 1: A performance-based approach to sizing infrastructure
Massively multiplayer online games (MMOGs) are some of the most complicated software systems under development today, often requiring dozens of developers, hundreds of artists, and truly massive infrastructures. This article is the first in a series of articles that will shine a light on the systems, storage, and networks needed to run an MMOG. It provides an introduction to MMOGs and demonstrates one approach to sizing a game's infrastructure. Learn how to figure out how much infrastructure you might need, as well as how to operate an MMOG. |
|
Articles |
|
10 Apr 2007 |
|
| |
The Power Architecture Time Base register in 64-bit Linux
Use the Power Architecture technology's Time Base register to measure time at the nanosecond level in Linux on PowerPC and Cell Broadband Engine (Cell/B.E.) microprocessors. Applications where this is useful include timestamping transactions (typically encrypted or digitally signed single-use messages), profiling code, and implementing small, precise software delays. |
|
Articles |
|
04 Apr 2007 |
|
| |
Programming high-performance applications on the Cell/B.E. processor, Part 6: Smart buffer management with DMA transfers
Explore the concepts of double-buffering and multibuffering to improve code speed by parallelizing processing and data transfer, and allowing the SPE's memory flow controller (MFC) to coordinate the best order of operations for loading and storing. |
|
Articles |
|
03 Apr 2007 |
|
| |
An introduction to the IDE for the Cell Broadband Engine SDK
This introductory walk-through, updated for the Cell Broadband Engine (Cell BE) SDK V2.1, explores the Cell BE processor IDE and offers a click-for-click lesson on how to construct a simple project. |
|
Tutorial |
|
30 Mar 2007 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 4: The battle to make the virtual cabinets work
Nothing is as easy as one might hope. Since the last article was posted, the Heath Robinson Rube Goldberg (HRRG) Computer team has been battling every step of the way to bring the HRRG emulator's virtual cabinets online. On the way, we've re-engineered everything several times, and run across some unanticipated scenarios... |
|
Articles |
|
20 Mar 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 4: Program the SPU for performance
Write optimal code for the Cell Broadband Engine (Cell BE) processor's synergistic processing unit (SPU) and have your programs running lightning fast. This installment of "Programming high-performance applications on the Cell BE processor" covers SIMD vector programming, branch elimination, loop unrolling, instruction scheduling, and branch hinting techniques. Previous installments have covered the basics of the Sony PLAYSTATION 3, the Cell BE architecture, and SPU programming. |
|
Articles |
|
06 Mar 2007 |
|
| |
Assembly language for Power Architecture, Part 4: Function calls and the PowerPC 64-bit ABI
The ABI, or Application Binary Interface, is the set of conventions that allow
programs written in different languages or compiled by different compilers to call each
other's functions. This article, the last in a four-part series, discusses the
PowerPC ABI for 64-bit ELF (UNIX-like) systems and how to write and call functions using it.
Knowing in detail how the 64-bit PowerPC ABI works will help you write 64-bit programs
for the POWER5 and other PowerPC-based processors more effectively, whether you program
in assembly language or not. There is also a 32-bit ABI that is not covered in this article.
|
|
Articles |
|
28 Feb 2007 |
|
| |
Xilinx hijinx, Part 2: Building and loading bitstreams and PowerPC code
Explore both the hardware and software sides of a complete Virtex4 project. In this second and final installment of the Xilinx hijinx series, you add and remove device cores from your project, interconnect project components, build the bitstream, integrate it with C code, and download the entire thing to the FPGA. |
|
Articles |
|
22 Feb 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 3: Meet the synergistic processing unit
Continue looking in depth at the Cell Broadband Engine (Cell BE) processor's synergistic processor elements (SPEs) and how they work at the lowest level. This installment explores storage alignment issues and the communication facilities of the SPEs. |
|
Articles |
|
22 Feb 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 2: Program the synergistic processing elements of the Sony PLAYSTATION 3
Take even greater advantage of the synergistic processing elements (SPEs) of the Sony PLAYSTATION 3 (PS3) in this installment of "Programming high-performance applications on the Cell BE processor." Part 1 showed how to install Linux on the PS3 and explored a short example program. Part 2 looks in depth at the Cell Broadband Engine processor's SPEs and how they work at the lowest level. |
|
Articles |
|
07 Feb 2007 |
|
| |
Xilinx hijinx, Part 1: The ML403 out-of-box experience
Discover reasons you might choose an FPGA-based system over a traditional hard-IP microcontroller, and identify the learning curve traditional programmers face when meeting RAM-based programmable logic for the first time. In this new series, Lewin Edwards unpacks the Xilinx ML403 Embedded Development Kit and sorts out some of its idiosyncrasies. |
|
Articles |
|
30 Jan 2007 |
|
| |
SoC drawer: SoCs and the digital content revolution
SoC (system-on-a-chip) architectures could significantly accelerate digital video processing and enable the digital video revolution. Sam Siewert offers an overview of digital video processing and emergent applications in the video realm and shows how SoCs can uniquely accelerate processing. If you're an SoC architect, developer, Power Architecture platform software developer, or anyone creating digital video applications and services, this article is for you. |
|
Articles |
|
17 Jan 2007 |
|
| |
Assembly language for Power Architecture, Part 3: Programming with the PowerPC branch processor
The last two articles discussed the outline of how programs on the POWER5 processor work using the 64-bit PowerPC instruction set, how the PowerPC instruction set addresses memory, and how to do position-independent code. This article focuses on the very powerful condition and branch instructions available in the PowerPC instruction set.
|
|
Articles |
|
17 Jan 2007 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 3: Introducing the HRRG emulator
The continuing effort to add at least one series of (vacuum) tubes to the Internet progresses with an introduction to the workings of and thinking behind the Heath Robinson Rube Goldberg (HRRG) emulator. And stay tuned because next time you'll get to download it. |
|
Articles |
|
10 Jan 2007 |
|
| |
Programming high-performance applications on the Cell BE processor, Part 1: An introduction to Linux on the PLAYSTATION 3
The Sony PLAYSTATION 3 (PS3) is the easiest and cheapest way for programmers to get their hands on the new Cell Broadband Engine (Cell BE) processor and take it for a drive. Discover what the fuss is all about, how to install Linux on the PS3, and how to get started developing for the Cell BE processor on the PS3. |
|
Articles |
|
03 Jan 2007 |
|
| |
Assembly language for Power Architecture, Part 2: The art of loading and storing on PowerPC
The previous article in this series introduced assembly language programming
using the 64-bit PowerPC instruction set on POWER5 and other processors that use
these instructions. This article drills down and discusses the specifics of 64-bit
PowerPC assembly language programming on Linux and UNIX-like operating systems,
focusing on data access methods and position-independent code. |
|
Articles |
|
29 Nov 2006 |
|
| |
Tuning the CPC945 memory controller
|
|
Articles |
|
21 Nov 2006 |
|
| |
Don't let these disasters happen to you: A pox on modern engineering, Part 2
While per-transistor failure rates may be down, overall reliability hasn't declined as much as people sometimes assume, and modern systems are often much harder to repair than older ones. Following up on a previous article, Lewin Edwards reviews more of the problems modern engineers face. |
|
Articles |
|
14 Nov 2006 |
|
| |
The Heath Robinson Rube Goldberg Computer, Part 2:
Partitioning the system
In Part 2 of the Heath Robinson Rube Goldberg (HRRG) Computer series, learn how to partition the system, trading off between implementation complexity, granularity, and flexibility, while also
minimizing the bandwidth required to communicate among the various modules. |
|
Articles |
|
08 Nov 2006 |
|
| |
Directions: IBM and partners open up the silicon supply chain with the Common Platform
Steve Longoria, IBM vice president of Semiconductor Platforms, discusses the collaboration among IBM, Chartered, and Samsung in the open Common Platform technology initiative, and how the move is shaking up the industry's traditional closed model. |
|
Articles |
|
26 Oct 2006 |
|
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Don't let these disasters happen to you: A pox on modern engineering, Part 1
Between IP litigation and ever greater demands for "baseline" functionality that requires licensing, developing new products has become a treacherous minefield for engineers to navigate. In this article, Lewin Edwards outlines some of the dangers which are making it harder for engineers to just get out there and build something. |
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17 Oct 2006 |
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SoC drawer: Eyes inside the silicon
Author Sam Siewert describes basic methods and tools that can provide eyes into the silicon for architects, designers, and engineers working with reconfigurable systems-on-chips (SoCs). SoCs like the Xilinx Virtex line provide a hybrid platform for hardware and software co-design and implementation of real-time services and digital signal processing. Hybrid SoCs employing Power Architecture technology-based software interfacing to highly customized hardware state machines can help designers unlock the power of application-specific hardware acceleration. The integration of the Power Architecture cores with reconfigurable logic provides a powerful prototyping and product platform for SoCs. This power can be better unleashed using trace, debug, and analysis tools to visualize and tune hardware and software interfaces and interaction. |
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10 Oct 2006 |
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Assembly language for Power Architecture, Part 1: Programming concepts and beginning PowerPC instructions
The POWER5 processor is a 64-bit workhorse used in a variety of settings. Starting with this introduction to assembly language concepts and the PowerPC instruction set, this series of articles introduces assembly language in general and specifically assembly language programming for the POWER5.
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03 Oct 2006 |
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The Heath Robinson Rube Goldberg Computer, Part 1: Implementing a computer using a mixture of technologies from relays to fluidic logic
Imagine a computer formed from a mixture of technologies ranging from relays to fluidic logic. Now imagine being able to create a single piece of such a computer (perhaps as small as a single word of memory) in the technology of your choice, and then using the Internet to run your masterpiece in conjunction with other portions of the system created by contributors located around the world! Author Clive (Max) Maxfield explains the creation of just such a computing engine and how you can be involved. |
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03 Oct 2006 |
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Linux on board: Inside the MediaMVP
As an MP3 and MPEG player, the Hauppauge MediaMVP lets you play digital media through your television set. As a tightly purposed embedded device, it is an excellent example of a compact Linux implementation on minimal hardware. |
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28 Sep 2006 |
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Taking OpenPower for a spin, Part 3: How to avoid having to port your code
Why is porting even hard? In this last article of the "Taking OpenPower for a spin" series, Peter Seebach looks at what kinds of issues are involved with portability from one architecture to another and contrasts APIs with hardware interfaces. |
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26 Sep 2006 |
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Taking OpenPower for a spin, Part 1: Exploring 64-bit development on POWER5
The OpenPower program offers free remote access to servers running 64-bit Linux on POWER5 processors. In Part 1 of the Taking OpenPower for a spin series, author Peter Seebach introduces the process of getting access to a system and compiling applications for it, both as 32-bit and 64-bit applications. He pays particular attention to issues unique to "guest" software development without root privileges -- something most Linux users have never had to do. |
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26 Sep 2006 |
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Taking OpenPower for a spin, Part 2: Porting issues in targeting 64-bit systems
In Part 2 of the Taking OpenPower for a spin series, Peter Seebach reviews code portability issues when porting to 64-bit systems, looking in particular at code and data portability, with concrete examples of some of the rare kinds of code that require real modification. |
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26 Sep 2006 |
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Testing and measuring the TAMS 3011, Part 6: Booting NetBSD on new hardware, the saga begins
Porting an operating system to new hardware can be a fairly easy process, or a fairly difficult one, depending on the issues you encounter. Peter Seebach walks you through his experience getting NetBSD running on a new board using existing hardware. |
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19 Sep 2006 |
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Standards and specs: XML: Half a standard is better than none
A pervasive misconception common today is that simply designing your file format around XML somehow makes it magically portable, extensible, and intelligible by other programs. Peter Seebach explains why using XML is only part of the story when you're designing an extensible file format. |
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12 Sep 2006 |
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Don't let these disasters happen to you: Five more engineering hints you'll rarely hear
Lewin Edwards presents five more engineering tips, this time aimed at smaller companies without the overhead, or support structures, of a larger organization. |
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05 Sep 2006 |
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Multifunction multimedia machine, Part 5: Remote control is the new local interface
Add a Web-based user interface to a previously developed multimedia client in this episode of the Multifunction multimedia machine series. Author Lewin Edwards looks both at user-interface and back-end design issues, and shows how local browser functionality is an interesting alternative to requiring a remote browser. |
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29 Aug 2006 |
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SoC drawer: SoC design for hardware acceleration, Part 2
In the SoC design for hardware acceleration series, author Sam Siewert migrates a simple C function to a SystemC specification that can be simulated and verified for ultimate implementation as a hardware function. Part 1 provided the C code and a general overview of video capture, streaming, and processing. Part 2 shows how hardware acceleration of emergent applications, such as video streaming, can benefit from system-on-chip (SoC) design and reconfigurable SoCs with hybrid C software and field-programmable gate array (FPGA)-based functionality.
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22 Aug 2006 |
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Standards and specs: Of RoHS and rushed standards
When the ex cathedra RoHS Directive came down, it was missing a
little crucial piece of information -- how manufacturers, distributors, and purchasers of parts could communicate to each other the RoHS status of every part. |
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15 Aug 2006 |
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Debugging Cell Broadband Engine systems
Software development for new architectures can be an intimidating prospect, but the Cell Broadband Engine (Cell BE) SDK 1.1 provides the debugging tools you need to tackle it for the Cell BE architecture. This article describes how to use new versions of the GNU Debugger (GDB) to diagnose problems in both PPU and SPU programs. |
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08 Aug 2006 |
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Don't let these disasters happen to you: The top five engineering hints you'll rarely hear
Lewin Edwards presents five engineering tips that are crucially important to successful product engineering, but which are rarely brought up in discussions of engineering practices. |
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01 Aug 2006 |
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Power Architecture directions: IBM Design Consulting teams and "collaborative innovation"
Lee Green, vice president, IBM Brand Values and Experience, discusses how the IBM Design Consulting Services (DCS) group came into being, how it works in virtual
teams with clients and other IBM customer and technical service groups, some innovative products resulting from this design collaboration, and how DCS helps IBM penetrate new markets. |
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01 Aug 2006 |
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Partition management with EWLM, Part 1: The basic rules
You've gathered performance data with the help of the IBM Enterprise Workload Manager (EWLM) -- now you're ready to exploit this data by enabling intelligent partition management of your AIX and Linux partitions running on IBM System p5 servers. In this first part of a two-part series, you get an introduction to logical partitioning. You're guided through the steps to set up your environment for EWLM partition management, and learn how to configure partitions. |
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25 Jul 2006 |
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Power Architecture directions: Brand-new brand for Power Architecture technology
Michael E. Sullivan of IBM discusses how Power Architecture technology is being reborn under Power.org as a community-driven architecture and brand inspired by the open-source Linux model. Learn what motivated the changes, what they will mean for customers and partners, and what the new logo symbolizes. |
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24 Jul 2006 |
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Partition management with EWLM, Part 2: Partition management in action
You've gathered performance data with the help of the IBM Enterprise Workload Manager -- now you're ready to exploit this data by enabling intelligent partition management of your AIX and Linux partitions running on IBM System p5 servers. Jump into the action by examining the topology of this test environment and the workload used, looking at the domain policy. Then, run the workload and observe the partition management actions taken by EWLM. |
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18 Jul 2006 |
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Power Architecture community
calendar: Chips, supercomputers, and mainframes all very cool
Read more about IBM's frozen chip and industry efforts to craft flexible circuits at room temperature, rumors of a Cell Broadband Engine (Cell BE)-based supercomputer and other Cell BE- and console-related news, plus: good news for Cobol programmers, and for DAC attendees, there is such a thing as a free lunch. |
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17 Jul 2006 |
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Power Architecture downloads and documentation: New Cell BE SDK, RFID IDE, and updates to FFT and Parallel ESSL libraries
Download the new Cell Broadband Engine (Cell BE) SDK 1.1, check the PowerPC materials declaration for RoHS data, gain hands-on experience programming Blue Gene, and more, in this edition of Power Architecture downloads and documentation. |
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14 Jul 2006 |
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Maximizing the power of the Cell Broadband Engine processor: 25 tips to optimal application performance
Unlike on conventional processors, you can achieve near theoretical-maximum performance for real applications on the Cell Broadband Engine (Cell BE) processor. For this, you must be aware of the Cell BE processor's architectural characteristics: get to know them better with these 25 tips to optimal application
performance. |
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27 Jun 2006 |
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Standards and specs: The Interchange File Format (IFF)
The IFF file format had many of the features still sought today in modern file formats. This month's Standards and specs looks at the IFF file format and the lessons it has for modern file formats, such as XML. |
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13 Jun 2006 |
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Testing and measuring the TAMS 3011, Part 5: Porting NetBSD to the TAMS 3011
Having looked at Linux and eCos support for the TAMS 3011 in the previous installments, Peter Seebach examines NetBSD support for it, which turns out to entail a certain amount of coding. |
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13 Jun 2006 |
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Power Architecture community calendar: Water-cooled microprocessors
The future of processor cooling might be in a new water jet
technique. Robot/CHECKUP service tells your iSeries where it could be
better automated. IBM partners to build cluster of software and hardware design
centers in Wales. Plus, take the new 18 Cell Broadband Engine online courses, don't miss
the next Design Automation Conference, meet with top EDA and test vendors
from the Pacific Rim, and catch The Hitchhiker's Guide to Verification and the Cell BE tech briefing. |
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09 Jun 2006 |
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Power Architecture downloads and documentation: Electromagnetic field solver toolkit
Download a set of tools to help you generate larger, more
accurate, higher-bandwidth models that high-end systems require to handle
increasing complexity and data rates. Grab a set of updates for the General
Parallel File System 2.3 and 3.1 so you can take advantage of the new IBM
System Storage DS4000 EXP810 support. In the library: Explore the features
of the CICS Transaction Gateway for z/OS 6.1, learn to craft Java
applications that will run on a System z mainframe, and check out this
checklist to keep from making IPL mistakes with z/OS. Plus, join other
experts and write a Redbook on AIX 5L on IBM System i, an SOA architecture
handbook for z/OS, and a Redbook on how to exploit IBM TS7510 Virtual Tape Library on
i5. |
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08 Jun 2006 |
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SoC drawer: SoC design for hardware acceleration, Part 1
System-on-chip (SoC) designs offer the opportunity to migrate functionality initially implemented in software and firmware into hardware acceleration engines and state machines. Reconfigurable SoCs based on processors in FPGA fabric, such as the PowerPC 405 in the Xilinx Virtex-4, provide a platform for rapid migration of functionality from PowerPC software and firmware to the FPGA logic. Configurable application-specific integrated circuit (ASIC) SoCs can be optimized similarly over product revisions as SoC ASIC roadmap configurations are defined. This article examines methods for software design, specification, and implementation that will simplify future efforts to offload software functionality to hardware. Basic video and image processing algorithms provide working example algorithms for this article and the next. |
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06 Jun 2006 |
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Power Architecture community calendar: Melting the terabit memory
The future of high-data-rate terabit memories might involve melting a polymer hole and then refilling it. Chips with a "curve" might suffer less stress fractures in casing and connections. Some IBM technologies are on the front lines of prediction and prevention of pandemics. Plus, attend a Cell Broadband Engine (Cell BE) technical briefing, learn to facilitate petroleum exploration with Blue
Gene, and catch The Hitchhiker's Guide to Verification and the Denali SoC workshops. |
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31 May 2006 |
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Power Architecture downloads and documentation: Handbook for Cell Broadband Engine programming
Download an extensive programming manual for the Cell Broadband Engine (Cell BE) processor. Test new high-performance supercomputing math functions without the overhead of conditional branches. Try out the new platforms the Extreme Cluster Administration Toolkit supports. In the library: Learn to configure a System z9 EC, uncover the full story on System z connectivity, arrange a BladeCenter Boot from iSCSI SAN, install Eclipse on Linux on POWER, and discover alternative Linux distributions for POWER5 systems. |
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31 May 2006 |
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Testing and measuring the TAMS 3011, Part 4: Interfacing with flash and avoiding file systems
The Z-machine interpreter is a benchmark for OS functionality and development environments. With the groundwork of porting curses accomplished in Part 3, this article shows you how to complete the Z-machine interpreter, setting it up to use flash memory to save state, without the newfangled luxury of a file system. |
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30 May 2006 |
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Power Architecture directions: Denali scales the heights of verification and testing for Power Architecture-based designs
Sanjay Srivastava, president and CEO of Denali Software, Inc., talks about his ten-year-old company's entry into the hardware verification arena, its partnership with IBM to develop verification and compliance software for designs using the CoreConnect on-chip bus, and how Denali works within Power.org to develop open standards. |
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30 May 2006 |
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Initializing memory efficiently on Power Architecture platforms
Learn to efficiently initialize memory on Power Architecture systems. Software Developer Carlos Cavanna compares simple loops clearing one byte at a time to more elaborate algorithms, including the DCBZ instruction to zero whole cache lines at a time. The article concludes with some rough performance numbers to help you tune your own applications. |
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23 May 2006 |
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Standards and specs: Lies, statistics, and benchmarks
Benchmarks can be an excellent tool for predicting performance and estimating requirements. They can also be misleading, possibly catastrophically so. Benchmark standardization helps distinguish between a good estimate and a meaningless number. |
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23 May 2006 |
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Power Architecture community calendar: Blades take a bite out of the world
Blades grow at an astonishing rate, make first feature film, and help out small businesses. The mainframe modernizing efforts of IBM are a big win on several fronts. East Fishkill 300mm fab shows how to raise chips right. Big Blue executive lays out a strategy for moving from POWER5 to POWER6. And two sets of seminars -- Denali on SoC and Mentor Graphics on The Hitchhiker's Guide to Verification -- kick off a summer of technology. |
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16 May 2006 |
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PowerPC processor tips: PowerPC 750GX DPPS facilities
In this three-part series-within-a-series, "PowerPC 750GX dynamic power-performance scaling," Dale Elson explores the use of special PowerPC 750GX facilities and an adaptive algorithm to decrease processor power dissipation whenever the full performance of the processor is not required. In Part 2: Review the 750GX characteristics and meet the dynamic power-performance scaling facilities, including phase-locked loops. |
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12 May 2006 |
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Power Architecture downloads and documentation: Specifications on RoHS materials
Download materials specifications of RoHS and reportable substances on the PowerPC 740 and 740L; the PowerPC 750, L, FL, FX, GL, GX, CX, CXR; the PowerPC 970FX; and the Alma2. Test drive the SiGMA toolkit to pinpoint problems in memory usage for scientific applications. And read an implementation guide on the Communication Server for z/OS, the Cadence yield-aware reference flow for the IBM and Chartered 90nm low-power Common Platform, and how to deploy mission-critical applications on Linux on POWER systems. |
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12 May 2006 |
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Meet the experts: Peng Wu and Alex Eichenberger on compilers and hardware constraints
Programming in high-level languages such as C is like crossing an ocean without spending time looking at the water. developerWorks spent an hour with two IBM Research Compiler programmers exploring the ecosystem that lies beneath the surface. |
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10 May 2006 |
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SoC drawer: SoC prognostication
Since its emergence about a decade ago, the SoC (system-on-a-chip) architecture has become the underlying architecture for many embedded systems and scalable supercomputers and is starting to find its way into general purpose computing as well. The SoC embodies what many believe to be the ultimate level of integration: an entire system on one chip. Moore's law and higher levels of integration made the SoC inevitable, but can this continue? And what's next? This article takes a step back to gain perspective on the SoC and to see where it is going in the future. Perhaps the more important question is: where should the highest level of integration be, and what will it enable 25 years from today? |
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05 May 2006 |
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Cell Broadband Engine processor DMA engines, Part 2: From an SPE point of view
The Cell Broadband Engine (Cell BE) architecture provides on-chip DMA capabilities between the PPE and the SPEs. Meet the SPE interface to the DMA capabilities of the processor, from channel allocation to communication. |
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02 May 2006 |
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