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An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory

Analyzing calling frequencies for maximum SPE partitioning optimization

Power Architecture editors, developerWorks, IBM
The developerWorks Power Architecture editors welcome your comments on this article. E-mail them at dwpower@us.ibm.com.

Summary:  Fifth and last in the "An introduction to compiling for the Cell Broadband Engine™ architecture" series, this tutorial discusses techniques for managing data in the local store of the Synergistic Processor Elements (SPEs) of a Cell Broadband Engine (Cell BE) processor. Learn particular techniques such as double-buffering and maintaining a reasonably efficient software cache.

View more content in this series

Date:  07 Feb 2006
Level:  Intermediate
PDF:  A4 and Letter (218 KB | 25 pages)Get Adobe® Reader®

Activity:  6069 views
Comments:  

That's all, folks!

Congratulations!

This tutorial ends this series looking at the compiler technology used to target the Cell Broadband Engine processor. For more ideas of things to read up on, see the Resources in this tutorial (and in the others).

Acknowledgement

This tutorial series is based on the original presentation Optimizing Compiler for the Cell Processor given at PACT 2005 by Alexandre Eichenberger, Kathryn O'Brien, Kevin O'Brien, Peng Wu, Tong Chen, Peter Oden, Daniel Prener, Janice Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, and Michael Gschwind of IBM Research.

This Part 5 is based on the section "Automatic Memory Management on the SPE."

Cell Broadband Engine is a trademark of Sony Computer Entertainment Inc.

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static.content.url=http://www.ibm.com/developerworks/js/artrating/
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ArticleID=98034
TutorialTitle=An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory
publish-date=02072006
author1-email=dwpower@us.ibm.com
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