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An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory

Analyzing calling frequencies for maximum SPE partitioning optimization

Power Architecture editors, developerWorks, IBM

The developerWorks Power Architecture editors welcome your comments on this article. E-mail them at dwpower@us.ibm.com.

Summary: Fifth and last in the "An introduction to compiling for the Cell Broadband Engine™ architecture" series, this tutorial discusses techniques for managing data in the local store of the Synergistic Processor Elements (SPEs) of a Cell Broadband Engine (Cell BE) processor. Learn particular techniques such as double-buffering and maintaining a reasonably efficient software cache.

View more content in this series

Date: 07 Feb 2006
Level: Intermediate
PDF: A4 and Letter (218 KB | 25 pages)Get Adobe® Reader®

Activity: 8268 views
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Before you start

About this tutorial

This series provides an understanding of the Cell BE architecture, a basic intuition for programming issues on it, insight into the compiler challenges presented by it, and an understanding of the techniques and solutions proposed by the IBM compiler.

Prerequisites

See the previous parts in this series:

Part 1: Overview: The Cell BE architecture and some of the issues faced in compiler design
Part 2: Optimizing for the SPE: Optimizations used on the SPEs, such as how the compiler translates scalar code for a vector-only processor
Part 3: Making the most of SIMD: How a compiler can effectively generate SIMD code for two different architectures (the SPE and VMX), accommodating the various technical constraints of the processors
Part 4: Partitioning large tasks: How the compiler, or the user, can divide tasks up between the SPEs and the main processor