The first time you sign into developerWorks, a profile is created for you. Select information in your developerWorks profile is displayed to the public, but you may edit the information at any time. Your first name, last name (unless you choose to hide them), and display name will accompany the content that you post.

All information submitted is secure.

The first time you sign in to developerWorks, a profile is created for you, so you need to choose a display name. Your display name accompanies the content you post on developerworks.

Please choose a display name between 3-31 characters. Your display name must be unique in the developerWorks community and should not be your email address for privacy reasons.

All information submitted is secure.

My developerWorks:

My notifications:

Sign out

Select a language:

An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory

Analyzing calling frequencies for maximum SPE partitioning optimization

Power Architecture editors, developerWorks, IBM

The developerWorks Power Architecture editors welcome your comments on this article. E-mail them at dwpower@us.ibm.com.

Summary: Fifth and last in the "An introduction to compiling for the Cell Broadband Engine™ architecture" series, this tutorial discusses techniques for managing data in the local store of the Synergistic Processor Elements (SPEs) of a Cell Broadband Engine (Cell BE) processor. Learn particular techniques such as double-buffering and maintaining a reasonably efficient software cache.

View more content in this series

Tag this!

Date: 07 Feb 2006
Level: Intermediate
PDF: A4 and Letter (218 KB | 25 pages)Get Adobe® Reader®

Activity: 5495 views
Comments:

Before you start

About this tutorial

This series provides an understanding of the Cell BE architecture, a basic intuition for programming issues on it, insight into the compiler challenges presented by it, and an understanding of the techniques and solutions proposed by the IBM compiler.

Prerequisites

See the previous parts in this series:

Part 1: Overview: The Cell BE architecture and some of the issues faced in compiler design
Part 2: Optimizing for the SPE: Optimizations used on the SPEs, such as how the compiler translates scalar code for a vector-only processor
Part 3: Making the most of SIMD: How a compiler can effectively generate SIMD code for two different architectures (the SPE and VMX), accommodating the various technical constraints of the processors
Part 4: Partitioning large tasks: How the compiler, or the user, can divide tasks up between the SPEs and the main processor

Comments

Close [x]

Help: Update or add to My dW interests

What's this?

This little timesaver lets you update your My developerWorks profile with just one click! The general subject of this content (AIX and UNIX, Information Management, Lotus, Rational, Tivoli, WebSphere, Java, Linux, Open source, SOA and Web services, Web development, or XML) will be added to the interests section of your profile, if it's not there already. You only need to be logged in to My developerWorks.

And what's the point of adding your interests to your profile? That's how you find other users with the same interests as yours, and see what they're reading and contributing to the community. Your interests also help us recommend relevant developerWorks content to you.

View your My developerWorks profile

Return from help

Close [x]

Help: Remove from My dW interests

What's this?

Removing this interest does not alter your profile, but rather removes this piece of content from a list of all content for which you've indicated interest. In a future enhancement to My developerWorks, you'll be able to see a record of that content.

View your My developerWorks profile

Return from help

static.content.url=http://www.ibm.com/developerworks/js/artrating/

SITE_ID=1

Zone=Multicore acceleration

ArticleID=98034

TutorialTitle=An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory

publish-date=02072006

author1-email=dwpower@us.ibm.com

author1-email-cc=