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An introduction to compiling for the Cell Broadband Engine architecture, Part 4: Partitioning large tasks

Divide and conquer: Parallelizing partitioned jobs

Power Architecture editors, developerWorks, IBM

The developerWorks Power Architecture editors welcome your comments on this article. E-mail them at dwpower@us.ibm.com.

Summary: This tutorial, fourth and penultimate in the "An introduction to compiling for the Cell Broadband Engine™ architecture" series, discusses ways to partition code to run across the multiple cores available in a Cell Broadband Engine™ (Cell BE) processor. It gives particular attention to efficient partitioning of code to allow larger programs or data sets to be manipulated using the 256KB of local store available on the Synergistic Processor Elements (SPEs).

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Date: 07 Feb 2006
Level: Intermediate
PDF: A4 and Letter (114 KB | 18 pages)Get Adobe® Reader®

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Before you start

About this tutorial

This series provides an understanding of the Cell BE architecture, a basic intuition for programming issues on it, insight into the compiler challenges presented by it, and an understanding of the techniques and solutions proposed by the IBM compiler.

Prerequisites

See the previous parts in this series:

Part 1: Overview: The Cell BE architecture and some of the issues faced in compiler design
Part 2: Optimizing for the SPE: Optimizations used on the SPEs, such as how the compiler translates scalar code for a vector-only processor
Part 3: Making the most of SIMD: How a compiler can effectively generate SIMD code for two different architectures (the SPE and VMX), accommodating the various technical constraints of the processors

And wrap up the series with Part 5:

Managing memory: Techniques used, by the compiler or the programmer, to give the SPEs access to data that can't fit in local storage

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TutorialTitle=An introduction to compiling for the Cell Broadband Engine architecture, Part 4: Partitioning large tasks

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