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An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE

Think of it as an opportunity, not a challenge

Power Architecture editors (dwpower@us.ibm.com), developerWorks, IBM

The developerWorks Power Architecture editors welcome your comments on this article. E-mail them at dwpower@us.ibm.com.

Summary: Second in the "An introduction to compiling for the Cell Broadband Engine architecture" series, this tutorial discusses specific issues in optimizing code to run effectively on the Synergistic Processor Elements (SPEs) in the Cell Broadband Engine™ (Cell BE) processor.

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Date: 07 Feb 2006
Level: Intermediate
PDF: A4 and Letter (165 KB | 20 pages)Get Adobe® Reader®

Activity: 6997 views
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Before you start

About this tutorial

The SPE unit is exceptionally powerful, but has very specific requirements to unleash that power. The SPE is single instruction, multiple data (SIMD) only, so all scalars have to be presented as vectors, and all vectors have to be aligned. The local store memory is single-port, and extreme data throughput can lead to instruction starvation without care to regularly fill the instruction buffer. Without branch prediction in Cell BE architecture, hints become critical to keeping the instruction buffer properly filled. Optimizing code for the even/odd dual-issue instruction logic is another performance tool. This tutorial discusses these issues and ancillary ones at length.

Prerequisites

This article presumes some basic familiarity with the architecture of the Cell BE, and some basic understanding of computer architecture. Readers who managed the previous tutorial should be fine.

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TutorialTitle=An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE

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