Before you start
About this tutorial
The SPE unit is exceptionally powerful, but has very specific
requirements to unleash that power. The SPE is single instruction, multiple data (SIMD) only, so all
scalars have to be presented as vectors, and all vectors have to be
aligned. The local store memory is single-port, and extreme data
throughput can lead to instruction starvation without care to
regularly fill the instruction buffer. Without branch prediction in
Cell BE architecture, hints become critical to keeping
the instruction buffer properly filled. Optimizing code for the
even/odd dual-issue instruction logic is another performance tool.
This tutorial discusses these issues and ancillary ones at length.
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Prerequisites
This article presumes some basic familiarity with the architecture
of the Cell BE, and some basic understanding of computer
architecture. Readers who managed the previous tutorial
should be
fine.
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static.content.url=http://www.ibm.com/developerworks/js/artrating/
SITE_ID=1
Zone=Multicore acceleration
ArticleID=97757
TutorialTitle=An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE
publish-date=02072006
author1-email=dwpower@us.ibm.com
author1-email-cc=