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An introduction to compiling for the Cell Broadband Engine architecture, Part 1: A bird's-eye view

Overview

Power Architecture editors (dwpower@us.ibm.com), developerWorks, IBM

The developerWorks Power Architecture editors welcome your comments on this article. E-mail them at dwpower@us.ibm.com.

Summary: Meet the Cell Broadband Engine™ (Cell BE) processor from a compiler-writer's perspective, and get a bird's-eye view of a number of the unique challenges it poses in this first tutorial of a five-part series. Part 1 provides useful background information relevant to the other tutorials in the series.

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Date: 07 Feb 2006
Level: Intermediate
PDF: A4 and Letter (91 KB | 16 pages)Get Adobe® Reader®

Activity: 10965 views
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Before you start

About this tutorial

This tutorial presents an overview of the concepts essential to understanding Cell Broadband Engine (Cell BE) architecture and how a compiler can implement solutions to automatically distribute code to the Synergistic Processing Elements (SPEs) of Cell BE architecture. It is based mainly on the experiences of IBM Research in creating the Octopiler optimizing compiler, but also includes input from the Visual Age XL compiler team; as a series, it should be useful to other compiler writers, but also to anyone who would like a clearer understanding of Cell BE architecture in general. It introduces the local store memory of SPEs, the instruction buffer, auto-SIMDizing code, and the software cache approach to accessing irregular data. Subsequent tutorials discuss these topics in greater detail.

The topics covered in this five-part series include:

Part 1: Overview: The Cell BE architecture and some of the issues faced in compiler design
Part 2: Optimizing for the SPE: Optimizations used on the SPEs, such as how the compiler translates scalar code for a vector-only processor
Part 3: Making the most of SIMD: How a compiler can effectively generate SIMD code for two different architectures (the SPE and VMX), accommodating the various technical constraints of the processors
Part 4: Partitioning large tasks: How the compiler, or the user, can divide tasks up between the SPEs and the main processor
Part 5: Managing memory: Techniques used, by the compiler or the programmer, to give the SPEs access to data that can't fit in local storage

Prerequisites

Basic familiarity with computer architecture is helpful, but nearly any programmer in possession of a fully functional brain should be able to follow along.

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TutorialTitle=An introduction to compiling for the Cell Broadband Engine architecture, Part 1: A bird's-eye view

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