Microprocessor themes of 2004
2004 was all about process and research. On the one hand was the struggle to find alternatives to lead solder, since lead will be banned from electrical and electronic equipment by EU legislation set to take effect on January 1, 2006 (WEEE/ROHS (Waste Electronic and Electrical Equipment / Restriction of Hazardous Substances); and because disposal of lead-containing waste in Japan already warrants a hefty surcharge.
On the other hand, practical, traditional-physics limitations in manufacturing (quality and yield issues) and operating (cooling, electron leakage, and so on) in ever-shrinking, more densely packed chips, prompted paths into the quantum computing world, requiring companies to experiment with materials as well as architecture and implementation. The long-awaited and much-debated tech including spintronics, the use of light instead of electricity for digital logic -- and even clockless CPUs -- all got more serious attention than heretofore. Nanotechnology and dual cores also took the stage, and everybody wanted to have some 90nm process.
A month-by-month glance at the microprocessor space shows these themes in finer detail. Each month begins with a brief summary to give context to the listed items.
In January, research gets off to a rousing start, especially research into new materials to thwart the problems that arise when you create smaller transistors and pack more of them in tinier areas -- problems such as electrical leakage and overheating. An openness that comes with adopting an open systems philosophy also seems evident as one chip manufacturer hires another to produce its microprocessors and several companies use chips from competitors in various products.
- Researchers at the Vienna University of Technology announce that strontium titanate is considered the best candidate to replace silicon dioxide since it should scale to smaller dimensions without losing its insulating properties and reduce electrical leakage in sub-100nm transistors.
- Berkeley University researchers create a silicon Metal Oxide semiconductor integrated circuit with nanotube transistors with unusual molybdenum interconnects (instead of copper or aluminum), rendering an interesting but unusable chip.
- The European Commission funds NanoCMOS, a project to develop 45nm and smaller integrated circuits with the goal to produce 45nm prototypes by 2005 (and 32nm versions soon after).
- Intel® funds start-up NanoSys to get a jump on developing inorganic logic circuits.
- Intel invests to perfect the difficult and expensive Extreme Ultraviolet Lithography mask technology for 32nm chip generation.
- American Technology Research predicts that Sun® and IBM® are well positioned to capture the 64-bit desktop market since both use the Opteron processor as an integral part of upcoming product lines and both have initiated flexible CPU roadmaps.
- Via hires IBM to produce its next-generation 90nm "Esther" chip.
- Intel produces IA-32 execution layer to increase performance of 32-bit applications on Itanium 2 64-bit processors.
New technologies and techniques for producing chips is a recurring theme in February, all with the goal of finding a consistent way to beat the emerging 90nm standard. Extreme Ultraviolet Lithography and immersion lithography are still the best candidates to beat the limitations except that cost at present is prohibitive.
Add-ons to chips show up as AMD incorporates network security to its Au1550 processor. As the year goes on, others will add features to chips. Two efforts showcase silicon-on-insulator techniques: A low-power Cell chip project entered into by IBM, Sony, and Toshiba; and the IBM PowerPC® 970FX, constructed by employing SOI, strained silicon, and copper wiring techniques.
- Resin containing too much red phosphorus causes circuits to short out; more than 1,000 tons of the defective resin have been shipped, having the potential to cause as many as a billion IC failures or even more.
- Speakers and attendees at the 2004 SPIE conference on microlithography note that cost issues may outstrip technical issues as the biggest obstacle to the adoption of post-193nm techniques such as immersion lithography and EUV.
- Intel researchers build a high-speed transistor-like device that can encode data onto a beam of light.
- AMD and SafeNet add network security to AMD's 32-bit Au1550 hardware and software which will be available in 333, 400, and 500 MHz versions, each of which uses less than one watt and supports most network security protocols.
- IBM announces a method of making low-power, high-performance chips by a combination of SOI, strained silicon, and copper wiring technologies; the first microprocessor to benefit from this combination of processes will be the 90nm, 64-bit PowerPC 970FX.
- Intel releases the 90nm Pentium 4 "Prescott" CPU.
- Intel confirms 64-bit "extensions" in Xeon and Prescott chips.
- Texas Instruments offers new OMAP 2410 and 2420 mobile ARM processors.
- VIA offers new tiny, low-dissipation, increased-speed, 1GHz Eden ESP10000 processor that runs at the same speed as Pentium 3.
- IBM announces "open collaboration" model for Power Architecture™ processors.
Spintronics, the ability to determine and alter the magnetic directional state of a particle, gathers momentum as a potential direction to increase data in a smaller space. Spintronics adds another set of data-setting variables: Instead of just being able to set data due to charge (positive or negative, 1 or 0), you can also set data due to magnetic positioning (up or down). This makes the concept of quantum computing a much more real proposition.
Research into new materials and old materials processed in new ways continues. Developers also struggle with common problems such as how to cool the ever hotter, denser microprocessors.
A Swedish company makes an Internet-capable paper computer (circuits are printed with conductive inks).
- Micron Technology is forced to scrap 10,000 wafers (3.5 million memory chips) due to production error.
- Magnetic silicon may make spintronics possible so data may be stored not only as a charge state (positive or negative), but also as a position state (up or down) -- allowing for more data storage in a smaller area.
- Purdue University researchers want to cool chips with a small electrical storm inside the computer. As current moves through the "micro-scale, ion-driven airflow" device, it would fan the chip with a cool breeze.
- A research team at T.J. Watson Research Center develops a simple, low-cost process to make very thin films of semiconducting materials that allow electrical charge to flow 10 times as easily as in traditional processes; the ability to dissolve higher-mobility materials in a liquid will enhance existing spin-coating processes.
- AMD changes core to Newcastle, reducing cache to increase yield of its new Athlon XP mobile chip models.
- Samsung signs up for the IBM, Chartered Semiconductor, Infineon alliance to collaborate on sub-100nm-integrated circuit development effort.
- Cypak AB produces a disposable paper computer: circuits are printed on paper using conductive inks.
Transistor technology takes a leap when the Taiwan Semiconductor Manufacturing Company (TSMC) makes a double gate transistor with 5nm gates. On the downside, many chip fabricators are smarting from the problems of migrating from a 130nm process to a 90nm one.
In research, reduction in size causes Moore's Law to increase to three and a half years (42 months). The nano-debate continues, but the majority still sees a pure CMOS future.
- At the 2004 VLSI symposium, TSMC announces the development of FinFET transistors (a double-gate device which improves drive current and reduces electrical leakage) with 5nm gates; 20nm transistors with a 5nm gate could lead to 10GHz microprocessors with billions of transistors.
- TSMC differentiates its production processes into two camps: advanced (0.13 micron, 90 and 65nm) and mainstream (0.15 to 0.5 micron).
- Migration to 130 and 90nm production create difficulties, delays, and losses for chip fabrication plants; problems include increased electrical leakage, power consumption, and heat generation, leading to a decrease in yield.
- Semiconductor International announces an amendment to Moore's Law, predicting that the time to double transistor density will eventually reach to 42-plus months (echoing the 1975 change of the law to 24 months by Moore himself).
- Intel announces it will remove 95% of the lead from its chips by year's end. [EU legislation is set to take effect in 2006 which bans lead from electrical and electronic equipment. --eds.]
- Georgia Institute of Technology's James Meindl advocates using carbon nanotubes as interconnects, optical interconnects, and thermal interconnects (in which cryogenically cooled liquids are pumped through ICs via microchannels) as solutions to the problems with with scaling IC interconnects and resistance-capacitance issues for the production of sub-100 microchips.
- FTM Consulting predicts nanotechnology market will grow to US$75 billion within the decade, facilitating the emergence of a commercial market for nanowires and nanotubes. Industry analysts remain nano-skeptics, with most pundits saying that pure CMOS will make nanostructures unnecessary.
- IBM works with Stanford University to develop post-silicon spintronics technology -- which uses magnetic states to add data density without appreciable energy dissipation -- for logic and storage applications.
- Microprocessor Report analyst Tom Halfhill claims Intel reverse-engineered AMD's 64-bit x86 extensions. If true, it could well be the first time that has Intel followed this practice.
- AMD announces efforts to remove lead from processors.
The US government invests in nanoimprint advances and new techniques to battle overheating, lithography limitations, and SOI unreliability. AMD introduces a buffer-overflow flag to its processors (and several competitors decide to support it). Sony starts testing Cell processors. We say goodbye to both AMD's Athlon XP and to the Intel Netburst architecture.
- IBM Microelectronics announces its 200 and 300mm foundries are operating at full capacity; it's fabricating the 64-bit POWER5™ and nVidia's GeForce 6800 GPU.
- At the International Electronics Forum 2004, Dr. Bernard Meyerson of IBM announces that traditional CMOS scaling has run its course (effectively ending between the 130 and 90nm modes); he wants companies to draw "innovation roadmaps," guides to such solutions as strained silicon, silicon-on-insulator, and multi-gate transistors.
- The National Institute of Standards and Technology (NIST) commits US$17.5 million to developing nanoimprint technology; Motorola Labs is one of the recipients.
- Zalman introduces the reserator, a simple system of pump, pipes, and water reservoir to cool CPUs. The reservoir is located outside of tower and is composed of anodized, anti-corrosion materials.
- Startup Lumarray announces it is planning to use MIT maskless Zone-Plate-Array Lithography technology to produce 45nm chips with 193nm optical lithography; ZPAL uses arrays of individually targetable photon beams to fabricate complex shapes and it should theoretically work with 157nm lithography and EUV to produce 20nm ICs (currently the company has set no availability date).
- United Microelectronics Company describes a process to increase transistor switching efficiency on SOI transistors. The technique could provide PMOS transistors a 30% increase in drive current compared to conventional body-grounded SOI transistors and could enhance SOI reliability, at least until multi-gate transistors are available.
- AMD introduces another security feature: a buffer overflow NX flag in its "Hammer" line of 64-bit processors. Intel, Transmeta, and VIA say they will also employ the "No eXecute" bit that keeps certain nefarious inserted code from being executed.
- IBM introduces0.13 micro, 276 million transistor, multiprocessing POWER5 for the iSeries servers.
- IBM bestows fellowships on two chip innovators: Phaedon Avouris, a pioneer in nanotechnology, constructed functional transistors on a single carbon nanotube molecule; David Harame spearheaded IBM's commercialization of silicon germanium all the way to its use in BiFET and BiCMOS technologies.
- Intel showcases sample Montecito cores for the Itanium 2 processor; speculation is that it plans to release the 90nm, dual-core processor as a multi-chip module due to its size (the company only gives 2005 as a potential release date).
- Sony starts testing the 90nm Cell processor.
- VIA introduces the x86 handheld Eve Mobile Gaming Console, essentially a small PC running XP; it contains a 533MHz Eden-N processor with low power needs and low heat generation. VIA plans for it to be an open system.
The Semiconductor Industry Association invests in nanotech to help companies compete in post-CMOS technologies. IBM experiments with germanium-on-insulator technology that could allow chips to communicate with other system components through rapid light pulses and introduces a timing flow method for 65, 90, and 130nm chips that could help minimize power consumption.
AMD completes the design of AMD 64 dual-core processors. Intel attempts to stop overclocking by introducing a sensor circuit that shuts the system down, but several motherboard makers thwart the "governor" -- this will be an endless back-and-forth struggle. Intel also completes its transition to the 90nm process.
- Berkeley electrical engineering professors Bob Brodersen and Borivoje Nikolic tout "energy performance optimization" transistors as a way to efficient CMOS systems that consume 35% less power but only slow switching speeds by 8%.
- The Semiconductor Industry Association proposes to create a Nanoelectronics Research Initiative to begin in 2005; the US$100 million-a-year initiative will focus on pre-competitive research and development to help U.S. corporations compete in post-CMOS technologies.
- IBM develops a high-speed photodetector based on germanium-on-insulator technology (GOI) that could allow chips to communicate with other system components through rapid light pulses.
- IBM introduces a timing flow method for 65, 90, and 130nm ASIC chips that should help minimize power consumption. Variation-aware time lets engineers account for the variables in custom chip design by analyzing the time it takes signals to pass between circuits.
- German 3D Chips site finds a bug in Opteron microprocessors (confused instruction ordering flaw can be fixed with updated BIOS).
- AMD presents the first x86 dual-core processors to the industry.
- IBM developschip design verification software that may shorten the design life cycle and produce higher quality chips.
- Cisco and IBM design and build a complex programmable custom chip for Cisco Carrier Routing System (CRS-1); ASIC chip is designed to route data, voice, and video through IP networks.
- In an effort to defeat greymarket chip remarkers, Intel integrates a circuit in 925-, 915-series motherboard "governor" chips that prevent overclocking. Motherboard manufacturers ASUS and Gigabyte attempt to foil Intel's overclock lock circuit using register manipulation bypass.
- Intel debuts the 64-bit, 90nm, 800MHz-bus Xeon "Nocona" processors, essentially completing its transition to the 90nm mode of production; Intel starts a 300mm production at wafer fabrication plant in Ireland.
- Intel collaborates with CollabNet to release the successor to BIOS firmware under the Common Public License (CPL). Codenamed "Tiano," the pre-boot firmware will be designed to handle more complex management and administrative tasks than BIOS is.
- Toshiba breaks through sub-100nm limitations and debuts a 22nm bulk-CMOS transistor with metal gates and raised source/gate extension to provide better drive current and less electrical leakage.
- At the 2004 Computex exhibition, Transmeta unveils the prototype 90nm Efficeon processors. The chip consumes almost no power when in sleep mode and uses LongRun software to tweak transistors to reduce electrical leakage.
Analysts say that only small percentage of fab plants use 300mm wafers which means there's a way to go before this process can be considered adopted. eFUSE technology lets processors respond to changing conditions and re-optimize their performance parameters on the fly.
- Only about 14% of total wafer capacity is 300mm wafers according to the organization International Technology Roadmap for Semiconductors.
- IBM introduces eFUSE chip-morphing technology that combines software algorithms and microscopic electrical fuses that allow chips to respond to changing conditions. Chips should be able to monitor and adjust their performance without human intervention.
- IBM announces its POWER5-enabled Virtualization Engine in the pSeries servers, allowing several virtual OS instances to be combined across processors and connection.
- Intel ships 3.6GHz Pentium 4 chips.
- Nocona's EM64T implementation returns flawed address space information when polled by boot-time CPUID, which keeps Linux™-based operating systems from booting in AMD64 mode.
- To make transition from Xeon to Itanium easier, Intel plans to design socket and bus technology that can work with both.
- Transmeta's 90nm Efficeon suffers delay as problems arise in transition to Fujitsu's 90nm process.
Efforts into bio-engineering of semiconductor materials are explored as another avenue to combat the problems of packing more in a smaller space. HP issues the last ever Alpha processor system. Toyota R&D fashions low-defect silicon carbide wafers, a substrate with properties that may help keep chips cool.
AMD demonstrates the first dual-core x86 processor. Sony debuts a 64-bit MIPS R4000 chip for Playstation Portable, a chip with drastically reduced power consumption needs. Convergence of multiple-vendor systems continues.
- Samsung announces that it will develop a 300mm wafer fabrication plant to build 65nm chips, the second such plant for the company; the company declined to speculate on where the plant will be built.
- Cambrios (formerly Semzyme Inc.) discloses plans to incorporate biologically engineered organisms into semiconductor manufacturing.
- Sirenza Microdevices announces the release of 32 silicon-germanium RF components in an effort to promote environmentally-friendly disposability.
- Toyota R&D researchers claim to have a method for building low-defect silicon carbide wafers (SiC), a semiconducting material with an extremely high 2,700-degree C melting point; MEMS, blue LEDs, and laser diodes are already built from it.
- AMD showcases the first x86 dual-core processor with four dual-core Opteron processors manufactured in the 90nm SOI process.
- Say goodbye to the Alpha, one of the earliest 64-bit architectures. HP confirms that the 1.3GHz EV7z release of this microprocessor will be the last.
- Freescale announce plans for a dual-core, mobile G4 processor for the low-power notebook market. The cores will be designed to scale to as much as >2 GHz.
- Sony announces that its PlayStation Portable will sport a modified, 64-bit MIPS R4000 chip. Originally manufactured on the 1 micron scale, the 90nm chip has been customized to reduce the power load from 5-plus volts to run in a variable environment of 0.8 and 1.2 volts.
TSMC incorporates immersion lithography techniques (for 90nm process on 300mm wafers) into production line, making it the first large-scale fabricator to take this technology out of the lab and into production. Spintronics gets a leap forward as an IBM Almaden research team discovers how to measure the energy necessary to flip the magnetic orientation of a single atom.
AMD's lead in workstation market (thanks to Opteron) causes HP to can 64-bit Itanium workstation production. Freescale demonstrates dual-core SOI PowerPC processors. Sun's UltraSPARC IV debuts multi-chip threading capabilities.
- TSMC debuts 193nm immersion lithography process to fabricate 90nm parts on 300mm wafers; to be put in production in October 2004, TSMC will be the first large-scale chip fabricator to incorporate this technology into its production line.
- The Interuniversity MicroElectronics Center -- the Belgian government's leading laboratory for researching microelectronics and nanotechnology -- establishes a collaborative research program designed to meet the challenges posed by process scaling. It will address decreasing the difficulty involved in printing vias (wires that connect two interconnect layers) while improving vias' electrical characteristics, and will look into nanotube production as well as spintronics.
- Almaden Research Center researcher Andreas Heinrich and team measure a fundamental magnetic property of a single atom -- the energy required to flip its magnetic orientation; this knowledge is critical to the potential new technology based on spintronics.
- Opteron processors have a great month: IBM announces the eServer™ 326 Opteron server that supports AMD's dual-core specification and also releases an enhanced Opteron cluster, the eServer 1350; Sun announces three Opteron-based systems, the Sun Fire V40z and the Java™ Workstations W1100z and W2100z; HP discontinues its 64-bit Itanium workstation production citing Opteron-based workstations in command of the market.
- IBM announces the Linux-based OpenPower 720 eServer. Powered by four 64-bit POWER5 processors, it is IBM's first entry-level priced POWER-based server ever. There are plans to introduce a dual-processor version in the first half of 2005.
- Freescale demonstrates seven dual-core PowerPC processors manufactured using a 90nm, SOI process; the chips, with the e500 and e600 PowerPC cores, are designed for embedded applications.
Although now becoming a de facto standard in fabrication, the transition to 90nm is not without its problems, and UMC's and TSMC's 90nm foundries struggle with the costs of the transition. Sun announces that after UltraSPARC IV+, it will deliver future chip fabrication to Fujitsu.
nVidia releases a chip with a hardware firewall and AMD patents a way to place a thermo-electric cooler into chipsets, and Intel cancels 4GHz Pentium 4 to focus on multi-core efforts.
- Two of the largest 90nm foundries, UMC and TSMC, report inconsequential returns from the technology because of the costs associated with it.
- nVidia releases nForce4, a chip that comes with a hardware-based firewall called ActiveArmor to keep the PC from becoming a zombie; the chip works with AMD's Athlon 64 and 64 FX and Sempron processors.
- AMD patents a method of placing peltier (a thermo-electric cooler, or TEC) into chip packages to make cooling 65nm processors easier. It uses current flow between different metals to cool junctions.
- IBM has a great month: IBM releases POWER5-based eServers p5-520 and p5-550 and xSeries servers based on Intel Xeon processors; it showcases Open Blade Server initiative by introducing the POWER-based eServer BladeCenter JS20 and the Xeon-based EM64T-based BladeCenter HS20; and it rolls out its giant killer 64-processor, POWER5-based eServer p5-595.
- Following the death of Netburst, Intel halts development of the 4GHz Pentium 4. Many on P4 development team moved to multi-core development.
- Intel announces the use of 90nm process to build IXP 23XX, a network processing unit that uses the XScale (ARM core) processor.
- At a press conference, Intel announces it plans to reach 45nm node by 2007 by using metal gate and low-k dielectric technologies; it plans to reach the 22nm level by 2012 by using conventional lithography, and predicts the end of current lithography techniques by 2014 (and the demise of CMOS scaling by 2020).
- Sun demonstrates a dual-core, 90nm UltraSPARC IV+. After shipping, the company plans to outsource the dual-core SPARC64 VI (2006) and the 65nm eight-core follow-up Niagara (2007) to Fujitsu.
Plastic electronics start to be considered for more uses, and Infineon demonstrates a new technique in which two chips are sandwiched together and interconnect among hundreds of surface contact pads.
ARM plans a design center in India. By 2008, China will knock Japan out of the top spot as consumer of chips.
AMD sees a bright future, and signs a second fabrication partner to start in 2006. IBM and Sony debut a Cell processor workstation; IBM also offers a commercial version of its Blue Gene supercomputer -- with dual-core POWER5 processors (the original uses dual-core 440s). Intel debuts Itanium Madison, probably its last 130nm chip. Texas Instruments makes plans to convert from 200 to 300mm wafer process.
- A congress in Germany is convened to discuss the ups and downs of plastics-based electronics; end result: they're still cheap, and still too slow.
- Infineon Technologies demonstrates the 1MB, 130nm, chip card SLE88CFX1M00P which showcases a new sandwiching technique in which two chips with different functions are stacked on top of each other and interconnect through hundreds of tiny contact pads on the chips' surfaces. Infineon hopes the technique will deliver higher performance with only marginally increased silicon area.
- Handshake Solutions debuts a clockless ARM processor core. Asynchronous computing cores have the potential to reduce power consumption, but chips might be hard to produce in volume.
- Due to expanding demand, AMD adds Chartered Semiconductor as a fabrication partner in 2006; will add fabrication partner to existing deal with IBM.
- Intel announces the Itanium Madison 9M. The cache-heavy will probably be Intel's last at 130nm.
- Intel names three Fellows: Stephen Pawlowski and Ian Young have been named senior fellows, and Timothy Deeter was named a fellow.
- The Chinese Semiconductor Manufacturing International Corp. (SMIC) qualifies its own 90nm process, developing the process independently.
- At the IEEE International Electronic Devices Meeting, IBM introduces strained germanium, a technique it claims can craft circuits that can lead to < 32nm devices by tripling the performance of today's silicon switches. Challenges of materials availability and process will have to be overcome in order to employ this technology in real life.
- International Data Corp. reports that over-supply of semiconductors will cause chip revenues to shrink by about 2% in 2005 after a 26% revenue growth in 2004. The report predicts that consumer electronics replacement cycle will clear out inventories, causing a rise in revenues again in the 2006-08 time frame.
- Freescale Semiconductor starts trading on the New York Stock Exchange (NYSE), beginning its new era as a fully independent company.
- IBM debuts the first silicon microprocessor based on an immersion lithography process, angling for circuit features as small as 45nm from 193nm tools.
- IBM Power RISC architecture spawns a 15-company open source initiative, Power.org. Included in the coalition are Cadence Design Systems, Chartered Semiconductor, Novell, Sony, and Synopsys.
- IBM debuts Cell processors, designed to be used in workstations, Sony PlayStations gaming consoles, and in Toshiba televisions. Programming the processor is said to be relatively easy.
- HP gives up on Itanium and sells its Itanium development team to Intel. As part of the deal, Intel will keep the several hundred engineers in the Colorado location.
Out with the old, in with the soon-to-be obsolete
Thanks for spending time with developerWorks this year. If you'd like to comment on events and happenings in the microprocessor space, please e-mail your thoughts and opinions to the Power Architecture editors. And don't forget to send in your microprocessor predictions for 2005 (see the sidebar, Looking ahead), and watch this space again next year to see if your predictions become history!
Here is looking forward to a great 2005!
- The twice-a-year 24th Top 500 List (Supercomputing Conference 2004) tracks and detects trends in high-performance computing by listing the 500 most powerful computer systems based on the best performance on the Linpack benchmark.
- One excellent source for microprocessor news and trends is ChipGeek.
- Another excellent source for chip information is the online journal The EETimes.
- To keep an eye on developments here at IBM, visit the IBM Microelectronics site.
- Read the developerWorks article, Great moments in microprocessor history for information on how the mircoprocessor arrived at its present-day configuration (developerWorks, December 2004).
- The Power.org standards consortium trying to create a broad environment of community members that are interested in participating in the Power Architecture structure.
- "Making the transition to 64 bits" (developerWorks, October 2004) covers some of the issues faced when porting existing 32-bit code to 64-bit with the 970FX.
- "Understanding 64-bit PowerPC architecture" (developerWorks, October 2004) looks at critical issues in IBM's 64-bit POWER designs.
- Have experience you'd be willing to share with Power Architecture zone readers? Article submissions on all aspects of Power Architecture technology from authors inside and outside IBM are welcomed. Check out the Power Architecture author FAQ to learn more.
- Have a question or comment on this story, or on Power Architecture technology in general? Post it in the Power Architecture technical forum or send in a letter to the editors.
- Get a subscription to the Power Architecture Community Newsletter when you Join the Power Architecture community.
- All things Power are chronicled in the developerWorks Power Architecture editors' blog, which is just one of many developerWorks blogs.
- Find more articles and resources on Power Architecture technology and all things related in the developerWorks Power Architecture technology content area.
- Download a IBM PowerPC 405 Evaluation Kit to demo a SoC in a simulated environment, or just to explore the fully licensed version of Power Architecture technology. This and other fine Power Architecture-related downloads are listed in the developerWorks Power Architecture technology content area's downloads section.
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