Historically, IBM® Power Architecture™ microprocessors have incorporated features to help users effectively manage power dissipation. The PowerPC® 750 microprocessor, produced in 0.25-µm technology, first gave users the options of dynamic power management, where execution units were not clocked when idle, and three software-selectable power-saving modes. The power-saving modes reduced functionality of other areas, with nap and doze modes limiting cache and bus snooping operations, and sleep mode turning off all functional units except for interrupts. These techniques were an effective way to reduce power, as they reduced switching on the chip.
As CMOS designs scaled down well, each successive shrink in technology provided an increase in density, allowing for a reduction in footprint or inclusion of additional features in the same space, all while yielding reduced power dissipation due to lower voltages, smaller geometries, and the CMOS device's characteristic of negligible standby power. This allowed the PowerPC 750L and PowerPC 750CXe offerings to increase frequency and features (like the on-chip L2 in the PowerPC 750CXe microprocessor) while reducing power dissipation with minimal extra design effort.
The 130-nm PowerPC 750FX microprocessor was the first IBM PowerPC microprocessor to provide hardware support for the concept of power savings through reduced frequency operation. The PowerPC 750FX microprocessor has dual-phase locked loops (PLLs) and supports software-initiated dynamic frequency switching operations; when both PLLs are locked, the frequency shift will complete in three cycles. This feature allows for full-on operation at reduced frequencies when power saving is more important, while providing the opportunity to quickly shift back to full-on high-performance mode when required. The PowerPC 750GX also includes this flexible feature.
As the process geometries have been reduced below 130 nm, power dissipation due to leakage currents has greatly increased. IBM addressed this challenge in the 90-nm PowerPC 970FX microprocessor by integrating strained silicon and Silicon-on-Insulator (SOI) into the same manufacturing process. This technique speeds the flow of electrons through transistors to increase performance and provides an insulating layer in the silicon that isolates transistors and decreases power consumption.
The PowerPC 970FX microprocessor also takes advantage of another new IBM-refined power-saving technique enabled through sophisticated system-wide tuning and controlling of processor frequency and voltage. This power-tuning method was described in a presentation at the International Solid-State Circuit Conference (ISSCC) in San Francisco, California, in February 2004.
The power-tuning feature of the PowerPC 970FX microprocessor helps enable a seamless, fine-grained, system-wide frequency and voltage change without stopping core execution units, disrupting interrupts, or disabling bus snooping. The frequency switch is not limited to the processor core, but also affects the processor bus and the bridge and memory controller support chip.
While the PowerPC 750FX/GX microprocessors have a dual-PLL design for frequency shifting, the PowerPC 970FX microprocessor has a single PLL, which is used to drive a divider circuit to produce multiple frequencies. This approach allows the PLL to stay locked to a given frequency while the processor core frequency is scaled dynamically. The divider circuitry drives a multiplexer, enabling the processor to switch to a new frequency within one cycle without phase shift. The PLL stays locked at full frequency because a secondary clock mesh, which is undivided, is used for feedback. This secondary, fixed-frequency clock mesh is also used for the power-tuning logic.
During the frequency switch, all of the processor logic is running except for the bus clocks. The design goal was to allow a switch from full speed to half speed from one cycle to the next. At a given frequency, different levels of operational modes exist, such as full-on, doze, and nap. From nap mode at a given frequency, a transition to a deep-nap mode at 1/64 the original clock speed is possible. Refer to Figure 1 to see the transitions supported by the PowerPC 970FX microprocessor power-tuning design.
Figure 1. Power-tuning modes (from ISSCC presentation by Dr. Cedric Lichtenau, IBM Boeblingen)
Within a system, all processors and the processor interfaces in the bridge chip are required to change frequency mode (except for deep-nap mode) concurrently. A processor can request the mode change by sending a special command over the processor interface to the bridge chip. The bridge grants the request, and in a multiprocessor system, mirrors this special request to the other processor and waits for all to signal that they have quiesced processor busses and are ready to switch modes. The bridge chip then triggers the mode switch. Because frequency scaling on the processor interface requires a change of some timing parameters, new parameters are sent along with the power-tuning command request and will overwrite the old parameters when the frequency switch occurs. No parameter change is required for a change to deep nap because the processor bus is not active in this mode.
When changing back to full frequency from a lower frequency, current rapidly increases, referred to as a high di/dt. A high di/dt can result in voltage droop on the processor die layer due to the parasitic inductance of the package and printed circuit board voltage distribution. To mitigate di/dt, the power-tuning control logic switches back and forth between the old and the new frequency, gradually running more and more cycles at the new frequency. The IBM designers refer to this technique as clock dithering.
The Power Architecture platform continues to offer innovative technology that maximizes performance and includes power-saving features that have evolved to handle the latest challenges. As chip structures become smaller and smaller, IBM's PowerPC team continues to work on innovative techniques to help offset power dissipation. To learn more about the PowerPC 970FX features and operation and more about the work IBM is doing on power management techniques, see the Resources section below.
- This article originally appeared in the June 2004 edition of the Power
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- For more information about power management in the PowerPC 970FX, see "The IBM PowerPC 970FX power envelope and power management," Norman Rohrer (developerWorks, September 2004).
- Read more about the development of the 970 FX in this interview with one of its creators.
- Learn more about the PowerPC 970 family.
- This Power Management Application Guide (in PDF format) will help you manage power consumption in earlier PowerPC models.
- IBM research has been working on dynamic power management for embedded PowerPCs.
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