As an SoC designer facing the challenges of today's advanced technologies, having a library of reusable, modular, and flexible embedded processor cores which enables you to make architectural decisions earlier in the design process can be the difference in getting your products to market quicker. The ability to quickly integrate and evaluate the cross-domain effects of design trade-offs on performance, power, timing, and die size can give SoC designers a huge advantage much earlier than was ever achievable with traditional design techniques. Embedded processors can help you accelerate innovation for your SoC design.
In general, embedded processors are useful for executing an infinite number of tasks based on a limited set of instructions that can combine to produce incredibly complex software programs running on single or multicore system implementations.
The IBM PowerPC® 405 32-bit reduced instruction set computer (RISC) processor core implements the Power Architecture™ technology with extensions for embedded applications. This core provides high performance and low power consumption while executing at sustained speeds approaching one cycle per instruction. On-chip instruction and data cache arrays can be implemented to reduce chip count and design complexity in systems and to improve system throughput.
The primary extensions of the PowerPC architecture defined in the embedded environment are:
- A simplified memory management mechanism with enhancements for embedded applications
- An enhanced, dual-level interrupt structure
- An architected DCR address space for integrated peripheral control
- The addition of several instructions to support these modified and extended resources
The PowerPC 405FX extends the Power Architecture technology with features to, among other things, enhance performance, integrate functionality, and reduce system complexity in embedded control applications.
Both the hard and the synthesizable implementations of the PowerPC 405 are a 32-bit general purpose RISC CPU with single-cycle execution of most instructions, including loads and stores at a sustained speed of up 600MHz with 1.52 DMIPS/MHz, 0.2mW/MHz, and 2 Sq.mm with 16KB/16KB cache.
|PowerPC 405||180nm CMOS Core||130nm CMOS Core||90nm CMOS Core|| Synthesizable Core |
|CPU Core Size (est. without cache)||1.4sq. mm||0.86sq. mm||0.52sq. mm||user defined|
| Performance |
|550 @300MHz||592 @ 390MHz||912 @ 600MHz||380 @ 250MHz|
|Power Dissipation (est.)||650mW @ 200MHz||500mW @ 266MHz||120mW @ 600MHz||400mW @ 250MHz|
|Voltage||1.8V +/-5%||1.5V +/-5%||1.2V +/-5%||1.5V +/-5%|
| I-Cache |
| 16K |
| 16K |
| 16K |
| 16K |
The PowerPC 405 processor core consists of a five-stage pipeline, separate instruction and data cache units, a virtual memory management unit (MMU), three timers, debug, and interfaces to other functions. The core provides a range of I/O interfaces that simplify the attachment of on-chip and off-chip devices. The PLB-compliant interface provides separate 32-bit address and 64-bit or 128-bit data buses for the instruction and data sides. This interface supports several methods of clock distribution and power management. The on-chip memory (OCM) interface supports the implementation of instruction- and data-side memory that can be accessed at performance levels matching the cache arrays. The Device Control Register (DCR) bus supports the attachment of on-chip registers for device control. These registers are accessed using the mfdcr and mtdcr instructions. Synchronous precise interrupts include most debug event interrupts, program interrupts, instruction and data storage interrupts, auxiliary processor unit (APU) interrupts, floating point unit (FPU) interrupts, TLB miss interrupts, system call interrupts, and alignment interrupts. Asynchronous precise interrupts include the critical and non-critical external interrupts, timer facility interrupts, and some debug events. Figure 1 illustrates the logical organization of the PowerPC 405.
Figure 1: Organization of the PowerPC 405
The Power Evaluation Kit (PEK) SoC design is constructed using modular, flexible, and reusable intellectual property (IP) core elements including a PowerPC 405 embedded processor model, an ethernet sub-system represented by the ethernet controller (EMAC), a media access layer (MAL) core with integrated receive and transmit FIFOs, a double data rate dynamic memory controller (DDR1), an external bus controller (EBC), a direct memory access (DMA) controller, an interrupt controller (UIC), and a UART. The cores are all connected to a hierarchy of on-chip buses including a high-speed processor local bus (PLB), a device control register (DCR) bus, and an on-chip peripheral bus (OPB). Figure 2 illustrates the logical organization of the PowerPC 405 based SoC design provided with the PEK V1.0.
Figure 2: PowerPC 405 block diagram for the PEK SoC design
The PowerPC 405 embedded processor core supports a wide range of hardware and software development tools. The IBM RISCWatch tool is an example of a development tool that uses the external debug mode, debug events, and the JTAG port to support hardware and software development and debugging. The RISCTrace feature of RISCWatch is an example of a development tool that uses the real-time trace capability of the processor core. This tool is provided with the PEK V1.0
The IBM PEK V1.0 available from developerWorks allows designers to evaluate, build, and verify SoC designs (see also the installation instructions). The first version of this kit is an SoC analysis framework which includes the IBM ChipBench™ System Level Design (SLD) tool and a set of IBM Open SystemC transaction-level architecture models for the CoreConnect™ IP cores. These models are designed to enable embedded software development and performance analysis for consumer applications based on Power Architecture technology.
The implementation phase of the target SoC design point may be done using one of several design flow options -- including a foundry flow, an ASIC flow, an RTL handoff flow, or a "turnkey" flow -- all while leveraging the same semiconductor platform.
This article provided a brief introduction to the PowerPC 405 core and the properties which make it a noteworthy candidate for integration into SoC designs for low-power consumer applications. To get to know the 405 even better, download the IBM PEK V1.0 from developerWorks.
After downloading the PEK, use the ChipBench System Level Design tutorial to create and simulate a design constructed from SystemC models of IBM PowerPC 4xx processor cores.
Read the PEK installation instructions.
Learn about SoC development service offerings from IBM Engineering & Technology Services.
Read about the PowerPC 405 instantiation in Virtex-II Pro and Virtex-II Pro X from Xilinx.
- Power Architecture specs
You may also want to consult the
Power Architecture specification, consisting of three parts:
- IBM PowerPC User Instruction Set Architecture, Book I
- IBM PowerPC Virtual Environment Architecture, Book II
- IBM PowerPC Operating Environment Architecture Book III
- You will find the
Programming Environments for 32-Bit Microprocessors similarly informative. That document is also made up of three main parts:
- IBM PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors (G522-0290-01)
- IBM The Programming Environments Manual for 64-bit Microprocessors
- IBM CoreConnect Specification including PLB4, PLB5, OPB, DCR on-chip buses
- Get to know the Processor Local Bus (PLB) and other IBM SoC framework architecture in the no-cost tutorial, SoC design with CoreConnect: 128-bit PLB explained (developerWorks, June 2005).
- You may also want to consult the Power Architecture specification, consisting of three parts:
- Quick Power Architecture links
- Check out the Power Architecture author FAQ or send a letter to the editor.
- Subscribe to the Power Architecture Community Newsletter.
- Peruse the developerWorks Power Architecture technology zone archives.
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