 | Level: Introductory Norman Rohrer (rohrern@us.ibm.com), Distinguished Engineer, IBM
27 Sep 2004
Updated 15 Oct 2004 For potent chips like the PowerPC 970 FX, power consumption is a real concern.This article looks at the power envelope for IBM's PowerPC 970FX processor to give you an understanding of the processor's power management techniques. See how the chip's power-tuning capabilities, along with the several power-saving modes available, allow for an overall reduction in power consumption.
The IBM® PowerPC® 970FX microprocessor covers a large frequency and power envelope using dynamic frequency and voltage scaling. This power-tuning allows you to quickly change the frequency from full frequency to f/2 and f/4 at a system level; for additional power savings, you can apply the resulting voltage reduction. A power envelope shows the complete range of frequency and power available for the microprocessor. In addition to the full frequency power-tuning capabilities, the power-saving modes of doze, nap, and deep nap reduce the power envelope, allowing for a reduction of average power consumption.
Total power calculations
As silicon technologies have scaled to smaller dimensions, the power of the processor has changed from solely ac switching power to a combination of leakage power and switching power. The implementation of the PowerPC 970FX microprocessor in a 90-nm technology reduces the switching power because of the reduction of capacitance due to chip size and a voltage reduction. The subthreshold leakage current, which is a small amount of current from any transistor that is supposed to be turned off, increases dramatically at the smaller dimensions. In addition, 90-nm technologies introduce a non-negligible amount of gate leakage power due to electrons tunneling through the gate oxide of the transistor to the silicon.
Figure 1 shows the total power of the processor and these three major components as a function of line center, where line center is the dimension of the transistor's gate. As the transistor is printed smaller or at a more negative sigma, the speed of the processor as well as the subthreshold leakage current increase.
Figure 1. Power as a function of the line center for gate leakage, subthreshold leakage, and switching power for 2.3 GHz, 1.2 V, and 85 degrees Celsius
Figure 1 represents the power at a fixed voltage of 1.2 V and a fixed frequency of 2.3 GHz. At this fixed voltage, the gate leakage power and the switching power are relatively unchanged. This total power is very sensitive to voltage. Each power component has a steep response to voltage; for example, ac switching power is proportional to V², whereas the subthreshold power is proportional to V³, and gate leakage power has an exponential relationship to voltage. As you decreases the voltage, both the power and frequency of the processor decrease as well, giving rise to dynamic frequency and voltage scaling to modify the power.
Maximum power envelope
The article "Frequency switching improves power management in Power Architecture chips" describes the power-tuning modes and state diagram of the PowerPC 970FX microprocessor (see Resources). The blue outline in Figure 2 shows a full theoretical range of power and frequency that can be obtained for the PowerPC 970FX microprocessor. (Please note that the numbers shown for the PowerPC 970FX processor are theoretical, and have not to date been confirmed by IBM or a third party in a real-world environment over the full voltage range.) The data within Figures 2 and 3 are projected curves. Products are not available over the complete voltage range.
Figure 2. Maximum power envelope from 0.8 to 1.3 V showing the power reduction possible through power-tuning methods
The lower-right portion of the curve shows the change in frequency and power from 0.8 to 1.3 V in 25-mV increments. The very top line of the envelope is the change in power at a fixed voltage of 1.3 V as the frequency decreases from 2.5 to 0 GHz, while the lowest line is at a fixed voltage of 0.8 V. These lines show the linear change in power following the ½CV²f power relation. The maximum power at a fixed voltage can be modulated by switching to the f/2 or f/4 mode. The reduction in frequency from 2.5 to 1.25 GHz to 625 MHz reduces the power from 100 to 75 to 60 W. At f/2 and f/4, a decrease in voltage can further reduce the power. The amount of power savings depends upon how far the voltage can be reduced. If the voltage can be reduced to 0.8 V, the power could be reduced to 15 and 10 W at f/2 and f/4, respectively. Today, a functional limitation exists in the 90-nm design, preventing operation below 1.0 V. This raises the lower edge of the power envelope from 0.8 to 1.0 V and the lower power line in our example to 27 and 19 W for f/2 and f/4, respectively. At the same time, the 1.3-V application condition can only be applied to products with less than 50,000 power-on-hours (POHs). To accommodate the reliability requirements of a 100,000-POH system, the upper voltage must be limited to 1.2 V.
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Nap power envelope
The lowest power states for the 970FX processor are the nap and deep nap modes. Nap mode occurs at the present operating frequency, whether it is f, f/2, or f/4. Deep nap is differentiated from nap mode by operating at f/64 and can be obtained from any of the three nap modes. Figure 3 adds the nap power envelope for the same voltage and frequency ranges at 65 C.
Figure 3. Maximum power and nap power envelopes showing transitions from maximum power to nap power at f, f/2, and f/4, and then to deep nap at f/64
The vertical arrows show the power reduction from maximum power to nap at 1.3 V. The horizontal arrows show the power saving dropping from nap to deep nap. At 1.3 V and 2.5 GHz, the power consumption is reduced from 100 W to less than 40 W in nap mode and less than 30 W in deep nap mode. At a reduced voltage of 0.8 V, the same nap and deep nap modes have a theoretical power of less than 5 W. Additional power savings can be achieved with process optimizations at the expense of reduced frequency.
Conclusion
The power envelope of the 970FX microprocessor shows the broad range of power and frequency that can be obtained with the use of dynamic frequency and voltage scaling for both maximum and nap power modes. Researchers at IBM will continue their work in these areas in order to improve chip performance.
Resources
About the author | 
| | Norman Rohrer is a Distinguished Engineer in the PowerPC Microprocessor Group within the System and Technology Group of IBM located in Essex Junction, VT. Norman received his Bachelor’s Degree in physics and mathematics from Manchester College, North Manchester, IN in 1987. He received his Master’s Degree and Doctor of Philosophy degree in electrical engineering from The Ohio State University, Columbus, OH in 1990 and 1992, respectively. Norman has been a lead designer on PowerPC 750 and 970 products for Apple’s G3 and G5 chips and Nintendo’s GameCube. His interests lie in the area of high-speed circuit optimization for future technologies. Norman holds 18 patents and is a co-author on two books titled High Speed CMOS Circuit Design Styles and SOI Circuit Design Concepts. He has been a Senior Member of IEEE since 2003. |
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