Level: Introductory Kane Scarlett (kane@us.ibm.com), developerWorks Editor, IBM
17 Apr 2007
Updated 19 Oct 2007 A quick-reference glossary of terms you might encounter when installing and using the Cell Broadband Engine™ (Cell/B.E.) processor SDK.
I hope this glossary of terms you're likely to encounter while using the Cell/B.E.
SDK Installation Guide and while programming for your processor will come in
handy— the terms were taken directly from the guide and
placed here as a quick reference. It will be updated periodically when new
information becomes available. Some of the entries point to more information
on the topic. If you find a term that has become important to you during
your Cell Broadband Engine processor training and implementation, please mail it to me for inclusion in this glossary.
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-- A --
Anaconda.
The main installation program for Fedora Core 6. (See this tip for a quick guide to installing FC6 for use with the Cell/B.E. SDK 2.1.)
AOS.
Array of structures. A method of organizing related data values. Also called vector-across form. See
SOA
.
atomic operation.
A set of operations, such as read-write, that are performed as an uninterrupted unit.
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-- B --
Barcelona Supercomputing Center.
Spanish National Supercomputing Center, supporting BladeCenter and Linux® on Cell/B.E.
BCS.
See
Barcelona Supercomputing Center
.
BE.
Broadband Engine. See
CBEA
.
BOOTP.
Bootstrap Protocol. A UDP network protocol used by a network client to obtain its IP address automatically.
Broadband Engine.
See
CBEA
.
built-ins.
A type of C and C++ programming language intrinsic that is similar to generic intrinsics, except that built-ins map to more than one SPU instruction. These intrinsics are prefaced by spu_.
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-- C --
cache.
High-speed memory close to a processor. A cache usually contains recently accessed data or instructions, but certain cache-control instructions can lock, evict, or otherwise modify the caching of data or instructions.
CBEA.
Cell Broadband Processor Architecture. A new architecture that extends the 64-bit PowerPC® architecture. The CBEA and the Cell Broadband Engine are the result of a collaboration between Sony, Toshiba, and IBM, known as STI, formally started in early 2001.
Cell/B.E.
Cell Broadband Engine. See
CBEA
.
Cell Broadband Engine Linux task.
A task running on the PPE and SPE. Each such task has one or more Linux threads and some number of SPE threads. All the Linux threads within the task share the task's resources, including access to the SPE threads.
Cell Broadband Engine program.
A PPE program with one or more embedded SPE programs.
CPI.
Cycles per instruction. Average number of clock cycles taken to perform one CPU instruction.
CPL.
Common Public License.
cycle-accurate simulation.
See
performance simulation
.
cycle.
Unless otherwise specified, one tick of the PPE clock.
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-- D --
DHCP.
Dynamic Host Configuration Protocol.
DMA.
Direct Memory Access. A technique for using a special-purpose controller to generate the source and destination addresses for a memory or I/O transfer.
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-- E --
EA.
See
effective address
.
effective address.
An address generated or used by a program to reference memory. A memory-management unit translates an effective address (EA) to a virtual address (VA), which it then translates to a real address (RA) that accesses real (physical) memory. The maximum size of the effective address space is 264 bytes.
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-- F --
FFT.
Fast Fourier Transform.
FIFO.
First In First Out. Queue type in which elements are processed in order of entry. See also
LIFO
.
FSF.
Free Software Foundation. Organization promoting the use of open source software such as Linux.
FTP.
File Transfer Protocol.
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-- G --
GCC.
GNU C compiler.
gdb.
GNU debugger. A modified version of gdb, ppu-gdb, starts a Cell Broadband Engine program. The PPE component runs first and uses system calls, hidden by the SPU programming library, to move the SPU component of the Cell Broadband Engine program into the local store of the SPU and start it running.
GPL.
GNU General Public License. Guarantees freedom to share, change, and distribute free software.
GNU.
GNU is Not UNIX®. A project to develop free UNIX-like operating systems such as Linux.
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-- H --
HTTP.
Hypertext Transfer Protocol. A method used to transfer or convey information on the World Wide Web.
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-- I --
I/O device.
Input/output device. From the viewpoint of software I/O devices exist as memory-mapped registers that are accessed in main-storage space by load/store instructions.
IDL.
Interface definition language.
ILAR.
IBM International License Agreement for early release of programs.
intrinsic.
A C-language command, in the form of a function call, that is a convenient substitute for one or more inline assembly-language instructions. Intrinsics make the underlying ISA accessible from the C and C++ programming languages.
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-- L --
L1.
Level-1 cache memory. The closest cache to a processor, measured in access time.
L2.
Level-2 cache memory. The second-closest cache to a processor, measured in access time. A L2 cache is typically larger than a L1 cache.
latency.
The time between when a function (or instruction) is called and when it returns. Programmers often optimize code so that functions return as quickly as possible; this is referred to as the low-latency approach to optimization. Low-latency designs often leave the processor data-starved, and performance can suffer.
libspe.
An SPU-thread runtime management library.
LIFO.
Last In First Out. Queue type in which elements are processed in reverse order of entry. See also
FIFO
.
Linux.
An open-source UNIX-like computer operating system.
LGPL.
Lesser General Public License. Similar to the
GPL
, but does less to protect the user's freedom.
local store.
The 256-KB local store associated with each SPE. It holds both instructions and data.
LS.
See
local store
.
LVM.
Logical volume manager. An abstraction of a physical hard disk.
LVM partition.
A portion of a physical drive managed by the LVM.
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-- M --
main memory.
See
main storage
.
main storage.
The effective-address (EA) space. It consists physically of real memory (whatever is external to the memory-interface controller, including both volatile and nonvolatile memory), SPU LSs, memory-mapped registers and arrays, memory-mapped I/O devices (all I/O is memory-mapped), and pages of virtual memory that reside on disk. It does not include caches or execution-unit register files. See also
local store
.
makefile.
A descriptive file used by the make command in which the user specifies: (a) target program or library, (b) rules about how the target is to be built, (c) dependencies which, if updated, require that the target be rebuilt.
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-- N --
NUMA.
Non-uniform memory access.
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-- P --
parallel array form.
See
SOA
.
PDF.
Portable document format.
performance simulation.
Simulation by the IBM Full System Simulator for the Cell Broadband Engine in which both the functional behavior of operations and the time required to perform the operations is simulated. Also called
cycle-accurate simulation
.
PERL.
Practical extraction and reporting language.
PowerPC.
Of or relating to the
PowerPC architecture
or the microprocessors that implement this architecture.
PowerPC architecture.
A computer architecture that is based on the third generation of RISC processors. The PowerPC architecture was developed jointly by Apple, Motorola, and IBM.
PPC.
See
PowerPC
.
PPE.
PowerPC Processor Element. The general-purpose processor in the Cell/B.E. chip.
PPSS.
PowerPC Processor Storage Subsystem. Part of the
PPE
. It operates at half the frequency of the
PPU
and includes a L2 cache and a Bus Interface Unit (BIU).
PPU.
PowerPC Processor Unit. The part of the
PPE
that includes the execution units, memory-management unit, and L1 cache.
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-- S --
sandbox.
Safe place for running semi-trusted programs or scripts.
scalar.
An instruction operand consisting of a single value.
SDK.
Software development toolkit. A complete package of tools for application development. The Cell/B.E. SDK includes sample software for the Cell Broadband Engine.
SIMD.
Single Instruction Multiple Data. Processing in which a single instruction operates on multiple data elements that make up a vector data-type. Also known as
vector processing
. This style of programming implements data-level parallelism.
SIMDize.
To transform scalar code to vector code.
SOA.
Structure of arrays. A method of organizing related data values. Also called parallel-array form. See also
AOS
.
SPE.
Synergistic Processor Element. It includes an SPU, an MFC, and an LS.
SPE thread.
A thread scheduled and run on an SPE. A program has one or more SPE threads. Each such thread has its own SPU local store (LS),.128 x 128-bit register file, program counter, and MFC Command Queues, and it can communicate with other execution units (or with effective-address memory through the MFC channel interface).
SPU.
Synergistic Processor Unit. The part of an SPE that executes instructions from its local store (LS).
spulet.
A standalone SPU program that is managed by a PPE executive.
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-- T --
tag group.
A group of DMA commands. Each DMA command is tagged with a 5-bit tag group identifier. Software can use this identifier to check or wait on the completion of all queued commands in one or more tag groups. All DMA commands except getllar, putllc, and putlluc are associated with a tag group.
Tcl.
Tool Command Language. An interpreted script language used to develop GUIs, application prototypes, Common Gateway Interface (CGI) scripts, and other scripts.
thread.
A sequence of instructions executed within the global context (shared memory space and other global resources) of a process that has created (spawned) the thread. Multiple threads (including multiple instances of the same sequence of instructions) can run simultaneously if each thread has its own architectural state (registers, program counter, flags, and other program-visible state). Each SPE can support only a single thread at any one time. Multiple SPEs can simultaneously support multiple threads. The PPE supports two threads at any one time, without the need for software to create the threads. It does this by duplicating the architectural state.
TLB.
Translation Lookaside Buffer. An on-chip cache that translates virtual addresses (VAs) to real addresses (RAs). A TLB caches page-table entries for the most recently accessed pages, thereby eliminating the necessity to access the page table from memory during load/store operations.
TRE.
Terrain Rendering Engine.
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-- V --
vector.
An instruction operand containing a set of data elements packed into a one-dimensional array. The elements can be fixed-point or floating-point values. Most Vector/SIMD Multimedia Extension and SPU SIMD instructions operate on vector operands. Vectors are also called SIMD operands or packed operands.
vector processing.
See
SIMD
.
Vector/SIMD Multimedia Extension.
The SIMD instruction set of the PowerPC architecture, supported on the PPE.
virtual memory.
The address space created using the memory management facilities of a processor.
virtual storage.
See
virtual memory
.
VNC.
Virtual Network Computing. A desktop-sharing system which uses the RFB (Remote FrameBuffer) protocol to remotely control another computer.
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-- W --
workload.
A set of code samples in the SDK that characterizes the performance of the architecture, algorithms, libraries, tools, and compilers.
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-- X --
XDR.
Rambus XDR DRAM memory technology.
xlc.
The IBM optimizing C compiler.
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-- Y --
yum.
Yellow dog Updater, Modified. A package manager for RPM-compatible Linux systems.
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About the author  | 
| | Kane Scarlett is the editor of the Power Architecture technology zone for developerWorks. His past publishing work was with such magazines as Unix Review, Advanced Systems, and the -World publications (Java-, Sun-, NC-, Linux-), as well as some little oddball journals like National Geographic Magazine. If you have any events, news, tips, or tools to mention, please contact him. |
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