 | Level: Intermediate Brad Frey (bradf@us.ibm.com), PowerPC Architect, IBM
10 Dec 2003
Updated 16 Nov 2005 This three-volume set defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions.
Book I: PowerPC User Instruction Set Architecture
- This Book defines the instructions, registers, and so on, typically used by application programs (for example, Branch, Load, Store, and Arithmetic instructions; general purpose and floating-point registers).
- All Book I facilities and instructions are non-privileged ( are available in problem state).
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Book II: PowerPC Virtual Environment Architecture
- This Book defines the storage model (caches, storage access ordering, and so on) and related instructions, such as the instructions used to manage caches and to synchronize storage accesses when storage is shared among programs running on different processors.
- All Book II facilities and instructions are non-privileged, but they are typically used via operating-system-provided library subroutines, which application programs call as needed. For example, to acquire or release a lock an application program _could_ use the appropriate Book II instructions directly, but instead typically calls a library subroutine to provide this service.
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Book III: PowerPC Operating Environment Architecture
- This Book defines the privileged facilities and related instructions (address translation, storage protection, interruptions, and so on).
- Nearly all Book III facilities and instructions are privileged. (Those that are non-privileged are described also in Book I or II, but only at the level needed by application programmers. For example, the description of the System Call instruction in Book I gives only the instruction format and the fact that the instruction calls the system to perform a service. Book III provides the complete description, including information needed by operating system programmers writing the corresponding service routines.)
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Additional information may be provided in other books that describe a particular processor implementation. Such books may describe approaches to obtaining the best performance, the results produced when a software error is encountered, and so forth.
Downloads | Description | Name | Size | Download method |
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| PowerPC Book I | pa-archpub1.zip | 870KB | HTTP |
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| PowerPC Book II | pa-archpub2.zip | 233KB | HTTP |
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| PowerPC Book III | pa-archpub3.zip | 585KB | HTTP |
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Resources
About the author | | | Brad Frey is currently Editor-in-Chief of POWER Architecture: PowerPC Processor. He joined IBM in Poughkeepsie, New York in 1984. There he developed custom processor performance models and was responsible for the system performance analysis of the last bipolar S/390® platform. In 1989, he took a system architecture position in Boca Raton to work on IA32 multiprocessing, interrupt and I/O architecture, and led technical exchanges with Intel®. In 1993, he took a system architecture position in Austin to bring industry standard design elements to the RS/6000® product line. He was chief engineer for two pSeries® low-end servers. You can contact him at bradf@us.ibm.com. |
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