An introduction to compiling for the Cell Broadband Engine architecture, Part 5: Managing memory

Level: Introductory

Power Architecture editors , developerWorks, IBM

07 Feb 2006

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Fifth and last in the "An introduction to compiling for the Cell Broadband Engine™ architecture" series, this tutorial discusses techniques for managing data in the local store of the Synergistic Processor Elements (SPEs) of a Cell Broadband Engine (Cell BE) processor. Learn particular techniques such as double-buffering and maintaining a reasonably efficient software cache.

In this tutorial

• Automatic memory management on the SPE
  
  
• Code partitioning: Automatic overlay management
  
  
• Execution of a partitioned SPE program
  
  
• Partition manager implementation
  
  
• Partitioning data
  
  
• Software caching in more detail
  

Prerequisites

See the other parts in this series:

• Part 1: A bird's-eye view
  
  
• Part 2: Optimizing for the SPE
  
  
• Part 3: Making the most of SIMD
  
  
• Part 4: Partitioning large tasks

System requirements

None

Duration

Under two hours

Formats

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