An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE

Level: Introductory

Power Architecture editors , developerWorks, IBM

07 Feb 2006

	Register now or sign in using your IBM ID and password.

Second in the "An introduction to compiling for the Cell Broadband Engine architecture" series, this tutorial discusses specific issues in optimizing code to run effectively on the Synergistic Processor Elements (SPEs) in the Cell Broadband Engine™ (Cell BE) processor.

In this tutorial

• SPE optimization overview
  
  
• Implementing scalar code on SIMD hardware
  
  
• Software-assisted branch architecture
  
  
• Software-assisted instruction issue
  
  
• Single-ported local memory
  

Prerequisites

This article presumes some basic familiarity with the architecture of the Cell Broadband Engine, and some basic understanding of computer architecture. Readers who managed the previous tutorial should be fine.

System requirements

None

Duration

Under two hours

Formats

Other parts in this series

• Part 1: A bird's-eye view
• Part 3: Making the most of SIMD
• Part 4: Partitioning large tasks
• Part 5: Managing memory

Share this.... Digg this story del.icio.us Slashdot it!

Back to top