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An introduction to compiling for the Cell Broadband Engine architecture, Part 2: Optimizing for the SPE

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Level: Introductory

Power Architecture editors , developerWorks, IBM

07 Feb 2006

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Second in the "An introduction to compiling for the Cell Broadband Engine architecture" series, this tutorial discusses specific issues in optimizing code to run effectively on the Synergistic Processor Elements (SPEs) in the Cell Broadband Engine™ (Cell BE) processor.

In this tutorial

  • SPE optimization overview

  • Implementing scalar code on SIMD hardware

  • Software-assisted branch architecture

  • Software-assisted instruction issue

  • Single-ported local memory

Prerequisites

This article presumes some basic familiarity with the architecture of the Cell Broadband Engine, and some basic understanding of computer architecture. Readers who managed the previous tutorial should be fine.


System requirements

None



Duration

Under two hours


Formats

html, pdf


Other parts in this series

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More in this series:
An introduction to compiling for the Cell Broadband Engine architecture